Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[Nothingness]

On the other hand, we have 20A coming out late this year. And 18A products shipping mid next year.

Process leadership in 2025 is happening after all.

I wouldn’t bet anything on Intel process at this point; do we have any clue that Intel new processes aren’t plagued by the current issues?

 

[Thunder 57]

This just in:

https://twitter.com/x/status/1814935845960581429

Apparently, there are no TSMC N2 products next year! Q4 2025 is way too late in the cycle.

On the other hand, we have 20A coming out late this year. And 18A products shipping mid next year.

Process leadership in 2025 is happening after all.

I'll believe Intel is prducing on new nodes when I see it. They don't have the best track record lately.

 

[CakeMonster]

I don't know how to vet this N2 info, but I've been wondering about N3* not being options for Z5 nor NV Blackwell consumer chips (nor Intel for that hatter if they need it). Will it take until N2 is actually shipping in large quantities before N3* is a cost effective alternative for anything larger than phone SoC's? (Which in this case is likely 2026 for the successors of the previously mentioned products)

 

[Nothingness]

A side note: Witeken is such an Intel apologist that I wouldn’t believe anything he writes about Intel or their competitors without carefully double-checking his claims first.

 

[jpiniero]

TSMC still says 2025 for N2 volume production, with no qualifier beyond that. H2 2026 for both N2P and A16 (which IIRC is just N2P with BSPD).

They also confirmed that N2 only has a measly 15% density increase for something that's surely going to cost a lot more than 15% compared to N3.

 

[Hitman928]

TSMC still says 2025 for N2 volume production, with no qualifier beyond that. H2 2026 for both N2P and A16 (which IIRC is just N2P with BSPD).

They also confirmed that N2 only has a measly 15% density increase for something that's surely going to cost a lot more than 15% compared to N3.

TSMC is quoting 15% chip density improvement. Logic density increase will be higher than that. I’m guessing that the SRAM and analog scaling is practically zero and is bringing down the chip density improvements while the logic density interment is still pretty good.

 

[lightisgood]

This just in:

https://twitter.com/x/status/1814935845960581429

Apparently, there are no TSMC N2 products next year! Q4 2025 is way too late in the cycle.

On the other hand, we have 20A coming out late this year. And 18A products shipping mid next year.

Process leadership in 2025 is happening after all.

The world's best process team has always been in Oregon.
In the last, TSMC didn't win but Intel did lose.

 

[SiliconFly]

I wouldn’t bet anything on Intel process at this point; do we have any clue that Intel new processes aren’t plagued by the current issues?

Intel new processes aren’t plagued by the *current* issues? What current issues? It's just FUD.

And you assume TSMC new processes aren’t plagued by the same *current* issues!!

Their entire panther lake lineup is on 18A. Intel has bet everything on 18A cos they're very confident that they'll deliver.

 

[oak8292]

Intel new processes aren’t plagued by the *current* issues? What current issues? It's just FUD.

And you assume TSMC new processes aren’t plagued by the same *current* issues!!

Their entire panther lake lineup is on 18A. Intel has bet everything on 18A cos they're very confident that they'll deliver.

An issue that Intel has that TSMC doesn’t have is the need for frequency and yield. Intel needs to beat the 14900KS in performance with yield to claim success for the Intel gamers. They have relaxed geometry on every node since 14 to improve frequency because IPC isn’t improving fast enough and desktop are delayed to second gen. That isn’ FUD, that is Intel.

Process design is too focused on frequency over power efficiency. Even back side power delivery is more about frequency. It will be expensive to implement and mobile doesn’t want it. That is why TSMC is bringing out GAA first and their version of back side power second.

Intel is focused on a small and shrinking market of gamers because that is where they get the most press. This may turn against them if they have binned too aggressively for frequency and failures are too high,

 

[Nothingness]

Intel new processes aren’t plagued by the *current* issues? What current issues? It's just FUD.

And you assume TSMC new processes aren’t plagued by the same *current* issues!!

That must be a conspiracy against Intel.

Their entire panther lake lineup is on 18A. Intel has bet everything on 18A cos they're very confident that they'll deliver.

They were very confident that they’d be OK with 14nm and 10nm.

Intel is now in the unpleasant position to prove their claims. Before their downfall everyone outside the semico world drank their Kool Aid. I’m not happy about that situation as I already wrote: sane competition is good. But at the same time I’m glad Intel is finally punished for having lied and having misbehaved for so long.

 

[SiliconFly]

That must be a conspiracy against Intel.

Ha ha... hilarious!

An issue that Intel has that TSMC doesn’t have is the need for frequency and yield. Intel needs to beat the 14900KS in performance with yield to claim success for the Intel gamers. They have relaxed geometry on every node since 14 to improve frequency because IPC isn’t improving fast enough and desktop are delayed to second gen. That isn’ FUD, that is Intel.

Process design is too focused on frequency over power efficiency. Even back side power delivery is more about frequency. It will be expensive to implement and mobile doesn’t want it. That is why TSMC is bringing out GAA first and their version of back side power second.

Intel is focused on a small and shrinking market of gamers because that is where they get the most press. This may turn against them if they have binned too aggressively for frequency and failures are too high,

It is FUD. There is absolutely no indication that 18A is a failure already. For all we know, Intel said it's progressing real well, and I too think so. In fact, it's in a better position that TSMC 2nm which itself has issues.

 

[mpumalanga]

Ha ha... hilarious!


It is FUD. There is absolutely no indication that 18A is a failure already. For all we know, Intel said it's progressing real well, and I too think so. In fact, it's in a better position that TSMC 2nm which itself has issues.

What are these 2nm issues TSMC is supposedly having ?
TSMC had some powerful statements regarding number of tape outs and maturity during their last quarterly call.

 

[Doug S]

A side note: Witeken is such an Intel apologist that I wouldn’t believe anything he writes about Intel or their competitors without carefully double-checking his claims first.

I've never seen TSMC claim "Q4" for N2. A lot of people (including me) had been assuming that though since Q4 is when N3B and N3E both began risk production and began mass production, and IIRC they have claimed "H2 2025" for N2 in the past. But hearing that N2 would enter risk production last week shakes things up, and coupled with the news that TSMC is pushing forward equipping their N2 lines for mass production at the very least calls up the possibility of A19 being fabbed in N2.

It would still be a stretch, and as I mentioned before it may require Apple being OK with entering mass production of A19 with yields below TSMC's standard 90% target. TSMC entered mass production of N3B (well) below that target because they'd already committed to making chips with it for Apple, but because they couldn't deliver on their end with standard mass production yields (that presumably Apple had been promised) they offered KGD pricing so Apple didn't have to eat the cost of the low yield.

If next year TSMC entered mass production of N2 below the 90% target, one would assume Apple would eat the cost of that reduced yield, if they were pushing TSMC to release it "early" this time. Given that the yield had already reached 80% two months ago, sub 90% yields would increase Apple's per die cost but we're talking a few dollars more in a device with a BOM well into the hundreds and an average ASP of nearly $1000. So given that risk production has already begun I very much believe Apple COULD be using N2 for A19. This may have been the reason behind the reported visit by Apple COO Jeff Williams early this year, where Apple supposedly secured all the initial N2 production. i.e. TSMC met various milestones in N2 development and reached a point where Apple was willing to commit to it and probably delivers a 10 digit prepayment. That resulted in TSMC pushing up equipping N2 lines to be ready, whether that mass production for Apple has yields at the 90% market or they only in the mid to high 80s.

Its also possible that the push for N2 isn't about A19, but about M5. That's lower volume and could come a month or two later in the year. Apple wouldn't need to push for an early start to mass production, TSMC could follow its normal schedule for Apple to have M5 Macs out by Christmas 2025. But unless N2 was going to ramp pretty slowly it is hard to see why that would require Apple buying out all the initial N2 volume as rumored.

In any case you're right about Witeken, and he's even dumber than I already thought he was if he expects anyone to believe TSMC is entering risk production in mid July with 80% yields and is pushing up equipping N2 lines but would still to stick to Q4 2025 even if that was something they had previously claimed. Like you say he's a big time Intel cheerleader and would like nothing more than for Intel to get 20A and 18A out while TSMC is still iterating N3.

 

[jpiniero]

The AMD talk about a future Epyc Dense being first on N2 made a lot more sense than Apple. The $/transistor is going to be horrifically bad.

 

[DrMrLordX]

Did the Chinese bribe TSMC to get to 7nm with DUV?

No, they (SMIC) beg/borrow/steal, which is something nobody outside of state-sponsored Chinese corporations can really afford to do for many reasons which should be obvious.

Apple could've invested in some expensive EUV machines, given them to GloFlo to experiment with and surely something would've come out of that gamble. $400 million isn't a lot for Apple, in order to ensure the future of their chips.

See above reply to your post, GF probably has EUV test equipment, yet they aren't doing anything with it commercially.

 

[jpiniero]

IIRC GloFo had EUV equipment but sold it.

 

[H433x0n]

I'll believe Intel is prducing on new nodes when I see it. They don't have the best track record lately.

Huh? Meteor Lake & Sierra Forest are both released. They've launched the Intel 4 /3 family of nodes.

 

[jpiniero]

Huh? Meteor Lake & Sierra Forest are both released. They've launched the Intel 4 /3 family of nodes.

The latter is more... launched... then released. Doesn't seem like you can buy a SF system yet.

 

[Doug S]

No, they (SMIC) beg/borrow/steal, which is something nobody outside of state-sponsored Chinese corporations can really afford to do for many reasons which should be obvious.

They reportedly made huge offers to some key TSMC people to help build the capability, and probably sent some people to get jobs at TSMC "undercover" as it were. But despite that and despite having more advanced DUV machines than TSMC did for their original N7, they still reportedly have rather poor yields with their 7nm.

In theory given those improved DUV machines they should not only be able to do a high yielding N7 class process, but potentially a high yielding N5 class process. There are so many angles where they could be falling short though, some that don't even have to do with the DUV capability at all (i.e. particulate filtration, wafer washing, vibration stabilization...all of which have finer and finer tolerances the denser you get)

I mean, look at Intel. They had a lot of process issues and reportedly a lot of their struggles had to do with multipatterning. TSMC made that look easy, but if you consider the insane tolerances required to make multipatterning work at the kind of scale required to launch new iPhone chips when the process is hot out of the gate, it is kind of amazing they were able to achieve such high yield mass production of N7 without EUV and without any schedule slip.

 

[jpiniero]

I mean, look at Intel. They had a lot of process issues and reportedly a lot of their struggles had to do with multipatterning. TSMC made that look easy, but if you consider the insane tolerances required to make that work, it is kind of amazing they were able to high yield mass production of N7 without EUV and without any schedule slip.

IIRC, TSMC just used relaxed pitch which basically avoided all the problems Intel had.

 

[FlameTail]

An issue that Intel has that TSMC doesn’t have is the need for frequency and yield. Intel needs to beat the 14900KS in performance with yield to claim success for the Intel gamers. They have relaxed geometry on every node since 14 to improve frequency because IPC isn’t improving fast enough and desktop are delayed to second gen. That isn’ FUD, that is Intel.

Process design is too focused on frequency over power efficiency. Even back side power delivery is more about frequency. It will be expensive to implement and mobile doesn’t want it. That is why TSMC is bringing out GAA first and their version of back side power second.

Intel is focused on a small and shrinking market of gamers because that is where they get the most press. This may turn against them if they have binned too aggressively for frequency and failures are too high,

Indeed. I read an article a few days ago which noted that Intel 3 has better performance (frequency) than TSMC N3, but the power and density is quite behind.

Has anyone else come across that article? It had bar charts and all comparing Intel 3 vs TSMC N3 and Samsung 3nm. I read it once, but I unable find that article.

 

[igor_kavinski]

I read it once, but I unable find that article.

Browser history?

 

[FlameTail]

Browser history?

It's not there.
Must have read it in Incognito.

 

[igor_kavinski]

This the one you read? https://www.szyunze.com/intel-3-higher-frequency-better-lithography/

 

[dttprofessor]

the power: intel 3 = tsmc n4
density： intel3 < tsmc n4