Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

---------------------------------------------------------------------------------------------------------------------------------------------------


FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[DavidC1]

the power: intel 3 = tsmc n4
density： intel3 < tsmc n4

Crestmont on N6: 1.46mm2
Crestmont on Intel 4: 1.01mm

N6 = 1.18% over N7, or 1.72mm2 Crestmont

TSMC claims 88% density improvement on N5, and N4 offers 6% improvement in density and Intel claims 10% increase in density with Intel 3 over 4.

TSMC claims N5 = 0.914mm2
TSMC claims N4 = 0.86mm2
Intel 3 = 0.92

However, Angstronomic data on Apple A14 shows the density gain on N5 is only 49%.

Angstronomic N5 = 1.15mm2
Angstronomic N4 = 1.08mm2

I don't think you can make the argument N4 is appreciably denser than Intel 3, maybe not even over Intel 4. Performance-wise Intel has always been superior. Power-wise it's probably a similar story to density.

 

[dttprofessor]

Crestmont on N6: 1.46mm2
Crestmont on Intel 4: 1.01mm

N6 = 1.18% over N7, or 1.72mm2 Crestmont

TSMC claims 88% density improvement on N5, and N4 offers 6% improvement in density and Intel claims 10% increase in density with Intel 3 over 4.

TSMC claims N5 = 0.914mm2
TSMC claims N4 = 0.86mm2
Intel 3 = 0.92

However, Angstronomic data on Apple A14 shows the density gain on N5 is only 49%.

Angstronomic N5 = 1.15mm2
Angstronomic N4 = 1.08mm2

I don't think you can make the argument N4 is appreciably denser than Intel 3, maybe not even over Intel 4. Performance-wise Intel has always been superior. Power-wise it's probably a similar story to density.

I correct:
Efficacy: intel 3= tsmc n4
Density: intel 3< tsmc n3
The difference on intel3/4 is beol,by now.

 

[lightisgood]

Efficacy: intel 3= tsmc n4

Never.

 

[dttprofessor]

Never.

You can compare gnr & turin few months later.

 

[SiliconFly]

It's good to see people comparing Intel 4/3 to TSMC N4/N3.

I know a guy who thinks 18A = TSMC N7.

 

[Nothingness]

It's good to see people comparing Intel 4/3 to TSMC N4/N3.

I know a guy who thinks 18A = TSMC N7.

And we know a guy who thinks Intel rulz da process world.

 

[DrMrLordX]

it is kind of amazing they were able to achieve such high yield mass production of N7 without EUV and without any schedule slip.

We'll probably never see execution like that again. Not from TSMC or anyone else.

 

[LightningZ71]

Well, don't forget that TSMC had a stepping stone towards N7 with their "10 nm" process. It wasn't quite as fast as it seems...

 

[igor_kavinski]

Page 667 - Discussion - Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

Page 667 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

Can HD libraries hit something like 5.7 GHz of Zen 5 fat cores?

 

[LightningZ71]

In a very generalized manner, you can push the frequency limits of the HD processes by deliberately leaving tiny amounts of dark silicon around critical paths and transistors as well as just adding extra transistors to a design to aid frequency scaling, especially on the most time limiting sections. It tends to quickly hit a break-even point with HP processes if you have to do this a lot of different places, but, AMD themselves have done some of this on past processors as they used TSMC's HD libraries on their high performance parts in the past.

As for specifically hitting that particular frequency with a particular process and a particular chip layout, that's a "secret sauce" question for the vendor.

 

[igor_kavinski]

Can HD and HP libraries be mixed in the same design, like the Zen 5 fat core (excluding caches and buffers)? Would doing so increase the lithography steps?

 

[ryanjagtap]

Can HD and HP libraries be mixed in the same design, like the Zen 5 fat core (excluding caches and buffers)? Would doing so increase the lithography steps?

Well N3E Fin-Flex is advertised as such, but I wouldn't know the complexity in designing such a product.

 

[Doug S]

Well N3E Fin-Flex is advertised as such, but I wouldn't know the complexity in designing such a product.

The tools would need to support it, and provide sufficient information that you know where you need them to close timing loops. So yes FinFlex allows it, but I'd love to see someone who has actually used it write an article about the experience and how much it helps and what the current limitations are. Maybe everything was in place so designers could use its full power from day one, maybe it will take years before they can truly exploit all it offers.

I wonder the same thing about BSPDN.

 

[poke01]

but they are also the ones who promoted TSMC to becoming a monopoly.

Carried over from the other thread.

Statements like these make no sense. TSMC became a monopoly thru merit. Because Intel and Samsung are incompetent. Kinda like how Steam is the default store for gamers. it’s easy to become the number one player when your competition is not as good as you are.

Apple, Qualcomm and Nvidia left Samsung because of their inability to produce enough quality nodes for future products.

 

[poke01]

tech insights had a article about N3E. Apple used HD and HP libraries together for the first time. Normally, Apple sticks to HD but with FinFlex it allowed them to use HP libraries for their performance cores allowing them to clock higher and HD for the efficiency cores and GPU.

Introducing TSMC N3E: The Power Behind Apple's M4 SoC | TechInsights

In a recent teardown of the Apple iPad Pro 11-inch, TechInsights revealed details of Apple's latest silicon: the Apple M4 SoC, codenamed TMRV93, built on TSMC's advanced N3E process. This surprise release demonstrates Apple's agility in adopting cutting-edge semiconductor technologies ahead of...

www.techinsights.com

 

[Doug S]

tech insights had a article about N3E. Apple used HD and HP libraries together for the first time. Normally, Apple sticks to HD but with FinFlex it allowed them to use HP libraries for their performance cores allowing them to clock higher and HD for the efficiency cores and GPU.

That's the most obvious and simplistic use case. What you should do is use HD libraries everywhere, and sprinkle in some use of HP in critical timing areas to increase Fmax. In terms of FO4 delay, you'd want to use HP transistors in places with the longest FO4 delay chain to shrink it, and repeat until you have so many similar "top" FO4 delays there's no point in continuing. This actually sounds like a good application for AI...

So Apple might be able to use HP rather than HD for their P cores and gain 10% but pay for it in power, but if they sprinkled HP cells around their design only where they are needed they might gain that 10% in both their P and E cores but pay almost no measurable penalty for power. But since they (apparently) didn't do so I'm assuming that's either difficult or impossible with current tools.

 

[igor_kavinski]

Kinda like how Steam is the default store for gamers. it’s easy to become the number one player when your competition is not as good as you are.

Not really a good example. They are not abusing their monopolistic position. They give back to the community and gamers by having regular crazy sales which has helped many gamers amass thousands of games in their libraries. TSMC probably only helps ARM garbage SoCs get cheaper. Their monopolistic prices are not helping matters when it comes to high performance CPUs.

 

[igor_kavinski]

So Apple might be able to use HP rather than HD for their P cores and gain 10% but pay for it in power, but if they sprinkled HP cells around their design only where they are needed they might gain that 10% in both their P and E cores but pay almost no measurable penalty for power. But since they (apparently) didn't do so I'm assuming that's either difficult or impossible with current tools.

Drop them an email. It's highly probable that it didn't occur to them to try something like that (not joking here).

 

[poke01]

TSMC probably only helps ARM garbage SoCs get cheaper. Their monopolistic prices are not helping matters when it comes to high performance CPUs.

I don’t know, if TSMC didn’t exist where would AMD and the rest etc get its designs manufactured?

Samsung? lol Intel? Give me a break!
N3E is expensive and it’s the amount of R&D that increased exponentially since N5 that they need to recoup.

It’s 100% Intels and Samsung fault that they cannot be good because of lack of talent and/or bad management.They get funding from governments and are still bad at producing Bleeding edge nodes in large quantities.

 

[poke01]

That's the most obvious and simplistic use case. What you should do is use HD libraries everywhere, and sprinkle in some use of HP in critical timing areas to increase Fmax. In terms of FO4 delay, you'd want to use HP transistors in places with the longest FO4 delay chain to shrink it, and repeat until you have so many similar "top" FO4 delays there's no point in continuing. This actually sounds like a good application for AI...

So Apple might be able to use HP rather than HD for their P cores and gain 10% but pay for it in power, but if they sprinkled HP cells around their design only where they are needed they might gain that 10% in both their P and E cores but pay almost no measurable penalty for power. But since they (apparently) didn't do so I'm assuming that's either difficult or impossible with current tools.

It is their first FinFlex try, let’s see if the design changes next year for M5. We got one year of FinFlex on N3P and then it’s NanoFlex in 2026.

 

[Doug S]

It is their first FinFlex try, let’s see if the design changes next year for M5. We got one year of FinFlex on N3P and then it’s NanoFlex in 2026.

I'm still not clear on exactly what NanoFlex is. It sounds like FinFlex, though maybe it is more flexible? The granularity of FinFlex was never that clear to me, maybe it was less granular than I thought and Nanoflex does what I thought/think FinFlex does? Is "short cells" and "tall cells" another way of saying "HD" and "HP" or is this something different? I never quite understood the interplay of # of tracks versus fin height, and now with GAA there aren't "fins" per se but it is the same sort of thing influencing drive currents, etc.

Anandtech could really use another Ian or Andrei to write an article explaining how this all fits together, and how much difference it makes. Is the 15% TSMC claims for Nanoflex independent of what FinFlex can deliver or is it a superset? Is it independent of HP and HD cells, or is that what they're calling "tall" and "short"?

One also has to wonder whether stuff like this is included in the nice little tables TSMC supplies that show us stuff like N3E vs N2 performance or power gains, or is this in addition to those gains? Hopefully the latter, we need everything we can get since Moore's Law sure isn't delivering the doubling every two years we got spoiled by for a long time.

 

[Thunder 57]

...Anandtech could really use another Ian or Andrei to write an article explaining how this all fits together, and how much difference it makes. Is the 15% TSMC claims for Nanoflex independent of what FinFlex can deliver or is it a superset? Is it independent of HP and HD cells, or is that what they're calling "tall" and "short"?

One also has to wonder whether stuff like this is included in the nice little tables TSMC supplies that show us stuff like N3E vs N2 performance or power gains, or is this in addition to those gains? Hopefully the latter, we need everything we can get since Moore's Law sure isn't delivering the doubling every two years we got spoiled by for a long time.

Ian jumped onto a lifeboat. Ryan is doing his best to turn AT into crap. I don't blame Dr. Cutress. The main page has gone downhill and if it weren't for the forums this site would be dead. But that's enough of the negatives.

 

[igor_kavinski]

It’s 100% Intels and Samsung fault that they cannot be good because of lack of talent and/or bad management.They get funding from governments and are still bad at producing Bleeding edge nodes in large quantities.

And Apple takes no blame for not trying to give them a sweet deal to motivate them, despite having more cash on hand than both of them combined?

13 Firms Hoard $1 Trillion In Cash (We're Looking At You Big Tech)

Cash is piling up fast on S&P 500 companies' books — and investors want their share.

www.investors.com

Yeah, no Intel no Samsung on that list.

 

[jdubs03]

Takes a long time to turn around a big ship!

 

[KompuKare]

And Apple takes no blame for not trying to give them a sweet deal to motivate them, despite having more cash on hand than both of them combined?

13 Firms Hoard $1 Trillion In Cash (We're Looking At You Big Tech)

Cash is piling up fast on S&P 500 companies' books — and investors want their share.

www.investors.com

Yeah, no Intel no Samsung on that list.

Don't forget that Intel until recently did lots of share buybacks. That is they artificially inflate the thing which the senior management and board have a huge stake in.

An engineering company - or any company - doing share buybacks says to me "we have run out of ideas", and in case of Intel it might also say that "we are not capable of diversifying outside our core market". The latter might be correct even.