Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

---------------------------------------------------------------------------------------------------------------------------------------------------


FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[poke01]

no Intel no Samsung on that list.

No need to. Intel is heavily funded by US and EU funding/subsidies.

Samsung literally has the South Korean Gov in the palm of its hand.

See, the state run bank will easily give the loan:

[News] Samsung Reportedly Seeks USD 3.6 Billion Loan from State-Run Bank for Chip Investment | TrendForce Insights

According to a report from Korean media outlet Korea Economic Daily (KED), South Korean tech giant Samsung Electronics is looking to borrow up to KRW ...

www.trendforce.com

 

[FlameTail]

I'm still not clear on exactly what NanoFlex is. It sounds like FinFlex, though maybe it is more flexible? The granularity of FinFlex was never that clear to me, maybe it was less granular than I thought and Nanoflex does what I thought/think FinFlex does?

It's simple:
FinFlex = FinFET
NanoFlex = NanoSheet

Nanosheet is what TSMC calls their version of GAAFET.

 

[FlameTail]

Dr. Ian Cutress [TechTechPotato] ; TSMC Technology Interview: A16 Node, System-on-Wafer, and High-NA

 

[Hitman928]

I'm still not clear on exactly what NanoFlex is. It sounds like FinFlex, though maybe it is more flexible? The granularity of FinFlex was never that clear to me, maybe it was less granular than I thought and Nanoflex does what I thought/think FinFlex does? Is "short cells" and "tall cells" another way of saying "HD" and "HP" or is this something different? I never quite understood the interplay of # of tracks versus fin height, and now with GAA there aren't "fins" per se but it is the same sort of thing influencing drive currents, etc.

Anandtech could really use another Ian or Andrei to write an article explaining how this all fits together, and how much difference it makes. Is the 15% TSMC claims for Nanoflex independent of what FinFlex can deliver or is it a superset? Is it independent of HP and HD cells, or is that what they're calling "tall" and "short"?

One also has to wonder whether stuff like this is included in the nice little tables TSMC supplies that show us stuff like N3E vs N2 performance or power gains, or is this in addition to those gains? Hopefully the latter, we need everything we can get since Moore's Law sure isn't delivering the doubling every two years we got spoiled by for a long time.

NanoFlex is just branding the same idea as FinFlex but for GAAFETs (i.e., NanoFlex is for nano sheets).

Tall cells are HP and short cells are HD. N3E allows for 3 different density/performance cell sizes, 3:2, 2:2, and 2:1. The size and performance decreases as you go down in number. Fin height is inherent in the process node and doesn't change with which standard cells you use. Track height is what changes with the number of fins you use.

For N3E, the "base" configuration would be 2:1 and is a shrink from the 2:2 of previous nodes. Then, they allow for a high performance 2:2 configuration or an ultra performance 3:2 configuration. The ultra performance is only 9% faster than high performance though, so the significant area increase isn't worth it for most. I'll try to write up more on it later today if I have time.

*Edit to correct the base/fin configuration information for N3E and previous nodes.

 

[maddie]

NanoFlex is just branding the same idea as FinFlex but for GAAFETs (i.e., NanoFlex is for nano sheets).

Tall cells are HP and short cells are HD. N3E allows for 3 different density/performance cell sizes, 3:2, 2:2, and 2:1. The size and performance decreases as you go down in number. Fin height is inherent in the process node and doesn't change with which standard cells you use. Track height is what changes with the number of fins you use.

For N3E, the "base" configuration would be 2:2 and is a shrink from 3:3 of previous nodes. Then, they allow for a higher performance 3:2 configuration or a higher density 2:1 configuration. The higher performance is only 9% faster though, so the significant area increase isn't worth it for most. I'll try to write up more on it later today if I have time.

I thought that Nanoflex has a continuous curve of transistor performance, versus Finflex, which has a step-function property.

 

[Hitman928]

I thought that Nanoflex has a continuous curve of transistor performance, versus Finflex, which has a step-function property.

That’s a difference between nanosheets and finfets, you’re still going to have discrete steps in standard cell sizes, that’s the whole point of standard cells.

 

[maddie]

nm

 

[maddie]

That’s a difference between nanosheets and finfets, you’re still going to have discrete steps in standard cell sizes, that’s the whole point of standard cells.

Nanosheets imply a wider choice of cells instead of using 1 fin, 2 fin, (X) fin transistors. Might there then be more libraries than merely HD, HP, etc, covering a more granular approach, or too much work for too little gain.

 

[Hitman928]

Nanosheets imply a wider choice of cells instead of using 1 fin, 2 fin, (X) fin transistors. Might there then be more libraries than merely HD, HP, etc, covering a more granular approach, or too much work for too little gain.

So, before finfets you could make transistors whatever width you wanted (within resolution and min/max limits) and standard cells were designed by track height, or basically how tall the cell was. From the standard cell libraries I've seen, there were usually like 3 or 4 different track heights to choose from. In addition to track height, there are also supply voltage and sometimes Vth options for the different track heights to choose from. So, if you have 3 track heights with 3 Vth options and 2 supply voltage options, the number of libraries you have to create becomes pretty big. Designing, characterizing, and validating a standard cell library is not easy and takes significant expertise, time, and money. So even with just 3 track heights, you already have 18 different libraries with all the different options that you have to characterize and validate. I don't think the cost to design more track height options is justified, even if the transistors themselves have much more flexibility in sizing, unless you are someone like an AMD, Intel, Apple, etc., that sell so many CPUs that customizing a standard cell library is worth it, as the cost ammortorized over the millions of units sold is probably small and lets you get exactly the cell you want.

 

[Hitman928]

I have edited my previous post to correct the fin configuration info for N3E. I remembered the fins wrong and TSMC had moved to 2:2 fins by N7.

 

[Doug S]

Fin height is inherent in the process node and doesn't change with which standard cells you use.

That I know is not true, the taller the fin the greater the drive current, and that's one of the knobs they use to distinguish between e.g. HD and HP.

 

[Doug S]

And Apple takes no blame for not trying to give them a sweet deal to motivate them, despite having more cash on hand than both of them combined?

So if there's a restaurant in your town that serves bad food, do you patronize them regularly so that they have the money to improve or do you keep going to the one that serves the best food in town? You gotta live by the rules you want to enforce on others!

 

[Aapje]

That I know is not true, the taller the fin the greater the drive current, and that's one of the knobs they use to distinguish between e.g. HD and HP.

Yeah, the taller fins take more space and thus lower density, but allow higher currents and thus higher frequencies.

 

[Hitman928]

That I know is not true, the taller the fin the greater the drive current, and that's one of the knobs they use to distinguish between e.g. HD and HP.

Well, I've worked in 2 finfet processes and neither had fin height as a parameter you could mess with. The fin height/shape is a very delicate thing from what I understand and not something the foundry will allow you to mess with at all.

Yeah, the taller fins take more space and thus lower density, but allow higher currents and thus higher frequencies.

Fin height is in a different plane, why would it take up more length/width? Standard cells increase fin number to increase current capability.

 

[Hitman928]

Well, I've worked in 2 finfet processes and neither had fin height as a parameter you could mess with. The fin height/shape is a very delicate thing from what I understand and not something the foundry will allow you to mess with at all.

@Doug S , I read your post again after not being distracted with other things and I misread a little bit what you were saying. I think a fab having, say 2 fin height options, for HD vs HP cells is something that is theoretically possible. However, the 2 finfet processes I have access to, I can say for sure do not offer this and I have not seen/heard of this being an option on any other process. The shorter fin height wouldn't save you any density, unless you were able to shrink the fin pitch and CGP with it, but I think that would add significant difficulty to the manufacturing process, which is probably why no one's done it. The shorter fin height, all else being equal, would decrease performance with the only benefit being a bit less gate capacitance and probably a tiny bit of leakage. I can't imagine it's worth the trouble when lower leakage at reduced performance can already be achieved by using a higher threshold device instead and FinFlex gives an alternative to the reduced gate capacitance benefit as well.

Fin height is in a different plane, why would it take up more length/width? Standard cells increase fin number to increase current capability.

Just to add here, besides number of fins, you can also use lower threshold devices to increase performance. The lower Vth devices won't take up any more area, but will have higher leakage.

 

[mikk]

18A 15% better perf/w over Intel 3, is this a mistake or maybe an updated projection? Previously it was +15% for 20A and additional 10% for 18A over 20A.

From here: https://t.co/ekKFSEid2G

From the same event:

Intel 18A is on schedule and expected to deliver an additional 10% improvement in performance per watt over Intel 20A.

https://www.intc.com/filings-reports/annual-reports/content/0000050863-23-000006/0000050863-23-000006.pdf

 

[SiliconFly]

PTL taped-out in 18A and running windows already. 18A on track.

 

[igor_kavinski]

PTL taped-out in 18A and running windows already. 18A on track.

How long do you think the track is gonna be there?

 

[SiliconFly]

How long do you think the track is gonna be there?

How long do you think the tracks usually are?

 

[igor_kavinski]

How long do you think the tracks usually are?

For Intel, unusually long and almost infinite, littered with excuses and delays. But now they face the brand new and UNPRECEDENTED prospect of having their track vanish into thin air!

By the way, if you haven't read it yet, Intel 4's yield issues for MTL are behind most of Intel's current financial woes and their grim outlook.

The Intel 4 you hyped to the moon.

 

[SiliconFly]

For Intel, unusually long and almost infinite, littered with excuses and delays. But now they face the brand new and UNPRECEDENTED prospect of having their track vanish into thin air!

Excellent! Kindly allow it to vanish into thin air.

 

[DavidC1]

By the way, if you haven't read it yet, Intel 4's yield issues for MTL are behind most of Intel's current financial woes and their grim outlook.

The Intel 4 you hyped to the moon.

Yes, but Intel 4 delay started long ago. That's why we had Raptorlake instead of Alder-->Meteor.

They delivered Intel 3 without a hitch.

Also Intel's claimed 1.3x density on 18A over Intel 3 is not a lot. They also said 14A is 1.2x density over 18A, which is again, very very small.

 

[FlameTail]

Also Intel's claimed 1.3x density on 18A over Intel 3 is not a lot. They also said 14A is 1.2x density over 18A, which is again, very very small.

Is that mixed SoC (50% logic, 30% SRAM, 20% analog) density gains or logic-only density gains?

TSMC quotes the above gains for Mixed SoC.

 

[jpiniero]

They delivered Intel 3 without a hitch.

Yeah, about that... doesn't appear you can actually buy a Sierra Forrest server, even if you wanted to. Lenovo has a datasheet about a theoretical server but it looks vaporish.

 

[DrMrLordX]

Yeah, about that... doesn't appear you can actually buy a Sierra Forrest server, even if you wanted to. Lenovo has a datasheet about a theoretical server but it looks vaporish.

That was expected. Intel (at least according to MLID's sources, guffaw) had some clients that drew a red line and said "deliver Sierra Forest by April 2024 or we buy from a competitor" and Intel had to deliver. So they did, but at what cost and in what volumes we'll never know. Sierra Forest is probably going to be unobtainium for a long time. The real question is: will Intel be able to deliver Arrow Lake-U? And will anyone really care?