Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[SiliconFly]

That was expected. Intel (at least according to MLID's sources, guffaw) had some clients that drew a red line and said "deliver Sierra Forest by April 2024 or we buy from a competitor" and Intel had to deliver. So they did, but at what cost and in what volumes we'll never know. Sierra Forest is probably going to be unobtainium for a long time. The real question is: will Intel be able to deliver Arrow Lake-U? And will anyone really care?

Intel mentioned a while ago that their wafer fab capacity (wafer starts per week) will double next year for Intel 4/3. Intel 20A is expected to hit significant volume mid next year (more than 4/3). Looks like they have allocated more EUVs to 20A/18A than to Intel 4/3. Sierra Forest availability will be a bit of an issue for a few more months at least.

 

[Ghostsonplanets]

The real question is: will Intel be able to deliver Arrow Lake-U?

Yes. Remember that they sold equity on Intel 3 fabs to Apollo and another one. So they're required to return these investments. Probably why a lot of upcoming products are on Intel 3.

I have no doubt ARL-U will exist at volume. Specially given Intel has already shipped 16M MTL and plans to ship 40M AI PC this year (MTL + LNL).

And will anyone really care?

That's a good question. It depends on pricing for ARL-U. It's certainly not a match for AMD Kraken and QCOM Purwa. So it will need to be priced lower and target a more budget segment.

 

[Doug S]

That was expected. Intel (at least according to MLID's sources, guffaw) had some clients that drew a red line and said "deliver Sierra Forest by April 2024 or we buy from a competitor" and Intel had to deliver. So they did, but at what cost and in what volumes we'll never know. Sierra Forest is probably going to be unobtainium for a long time. The real question is: will Intel be able to deliver Arrow Lake-U? And will anyone really care?

If they're really committed to pushing through on their 5 in 4 thing they can't afford to set up much production capability at the intermediate steps. They only have so many fabs able be outfitted for the leading edge, and only so many EUV scanners. So if the end goal is for 18A to be their first truly mass production foundry node, they can't be filling up one fab each with 4, 3 and 20A along the way. So if Intel 3 is limited in production capacity I can't say I'm surprised. They have other products committed to Intel 3 too, so they can't use it all for that one product.

We know Sierra Forest was targeted at cloud customers, but it might really have been targeted at hyperscalers only - maybe they just wanted to get something to keep the Amazons and Microsofts of the world happy to limit AMD and ARM gains in that market as much as possible. If they don't become more widely available until six months from now then they might announce whatever the 18A Sierra Forest will be called and hope enough customers decide to wait for it that they'll be able to serve the ones who need it now from their limited Intel 3 wafer runs.

 

[Geddagod]

NanoFlex is just branding the same idea as FinFlex but for GAAFETs (i.e., NanoFlex is for nano sheets).

Tall cells are HP and short cells are HD. N3E allows for 3 different density/performance cell sizes, 3:2, 2:2, and 2:1. The size and performance decreases as you go down in number. Fin height is inherent in the process node and doesn't change with which standard cells you use. Track height is what changes with the number of fins you use.

For N3E, the "base" configuration would be 2:1 and is a shrink from the 2:2 of previous nodes. Then, they allow for a high performance 2:2 configuration or an ultra performance 3:2 configuration. The ultra performance is only 9% faster than high performance though, so the significant area increase isn't worth it for most. I'll try to write up more on it later today if I have time.

*Edit to correct the base/fin configuration information for N3E and previous nodes.

The base HD cells are 2-1? I thought that was the finflex version with the base HD cell being 2-2.

18A 15% better perf/w over Intel 3, is this a mistake or maybe an updated projection? Previously it was +15% for 20A and additional 10% for 18A over 20A.

From here: https://t.co/ekKFSEid2G

From the same event:

https://www.intc.com/filings-reports/annual-reports/content/0000050863-23-000006/0000050863-23-000006.pdf

Prob an updated projection lol
It's unfortunate, but I still believe Intel 18A might have a small lead in perf/watt at mid-high voltages over N3. We will see with PTL vs LNL/ARL ig.

 

[ErichZannMusician]

NVIDIA is facing way bigger issues with Blackwell and is trying hard to save face:

Nvidia's Blackwell Reworked - Shipment Delays & GB200A Reworked Platforms

MGX GB200A NVL36, B102, B20, CoWoS-L, CoWoS-S, GB200A NVL64, ConnectX-8, Liquid Cooling vs Air Cooling, NVLink Backplane, PCB, CCL, Substrate, BMC, Power Delivery

www.semianalysis.com

Summary from u/Neofarm:

Tl;dr Nvidia encounters numerous setbacks at all levels trying to mass produce Blackwell. From interconnect between two dies of Blackwell at silicon level. To power delivery circuitry at board level. And power consumption/heat dissipation at rack level. Solution is selling more Hopper til next year. Unknown impact on revenue, margin for next couple Qs.

People have been saying for years that TSMC packaging will eventually be the limitation, and now it has come true.

This gives even more credence to the rumors that Intel Foundry, esp the packaging technology that Intel has, is on NVIDIA's radar as a backup plan.

 

[adroc_thurston]

People have been saying for years that TSMC packaging will eventually be the limitation, and now it has come true.

It's not a TSM issue at all.

 

[ErichZannMusician]

It's not a TSM issue at all.

Of course it is. In typical fashion, you talk ahead too much.

TSMC is constrained by shifting capacity from CoWoS-S (used earlier) to the more complex CoWoS-L, as well as physical issues in integrating the Blackwell dies on package.

 

[adroc_thurston]

Of course it is. In typical fashion, you talk ahead too much.

copium?

TSMC is constrained by shifting capacity to CoWoS-S

They built what was asked of them.

to the more complex CoWoS-L

It's not more complex, ASE/SPIL did FOEB eons ago.

as well as physical issues in integrating the Blackwell dies on package.

Yeah advanced packaging teams from places not AMD.
Expected.

 

[ErichZannMusician]

copium?

They built what was asked of them.

It's not more complex, ASE/SPIL did FOEB eons ago.

Yeah advanced packaging teams from places not AMD.
Expected.

Why are you even here after your Zen 5 "predictions"?


From the article:

CoWoS-L is a much more complex technology, but it is the future. Nvidia and TSMC aimed for a very aggressive ramp schedule to over a million chips a quarter. Consequently, there have been a variety of issues.

One is related to embedding multiple fine bump pitch bridges in the interposer and within an organic interposer can cause a coefficient of thermal expansion (CTE) mismatch between the silicon dies, bridges, organic interposer, and substrate, causing warpage.

The bridge die placement requires very high levels of accuracy, especially when it comes to the bridges between the two main compute dies as these are critical for supporting the 10 TB/s chip-to-chip interconnect. A major design issue rumored is related to the bridge dies. These bridges need to be redesigned. Also rumored is a redesign of the top few global routing metal layers and bump out of the Blackwell die. This is a primary cause of the multi-month delay.

There has also been the issue of TSMC not having enough CoWoS-L capacity in aggregate. TSMC built up a lot of CoWoS-S capacity over the last couple years with Nvidia taking the lion’s share. Now with Nvidia quickly moving their demand to CoWoS-L, TSMC is both building a new fab, AP6, for CoWoS-L and converting existing CoWoS-S capacity at AP3. TSMC needs to convert the old CoWoS-S capacity as otherwise it would be underutilized and the ramp of CoWoS-L would be even slower. This conversion process makes the ramp very lumpy in nature.

Combine these two issues and it’s clear that TSMC will not be able to supply enough Blackwell chips as Nvidia would like. Consequently, Nvidia is focusing what capacity they have almost entirely on GB200 NVL 36x2 and NVL72 rack scale systems. HGX form-factors with the B100 and B200 are effectively now being cancelled outside of some initial lower volumes.

 

[adroc_thurston]

Why are you even here after your Zen 5 "predictions"?

I like winning.
Gonna beat and raise Q3 too. God bless you Lisa.

From the article:

I know dolan, you don't have to quite him to me of all people.
It's an NV goof.

 

[Hitman928]

Why are you even here after your Zen 5 "predictions"?


From the article:

It says the 2 main issues are NV design problems. . . ?

 

[ErichZannMusician]

It says the 2 main issues are NV design problems. . . ?

There are problems at every level - which ones are you calling "2 main issues"?

 

[Hans Gruber]

One of Nvidia's problems is the density of the silicon required for Blackwell. N4X is the only TSMC 5nm silicon (TSMC calls it 4nm) that has enough silicon density to accommodate Blackwell's high end offerings well above 5090 GPU's and probably several lower variants from 5090. Nvidia wanted to be on 3nm but Apple bought all the 3nm silicon up on the first run and TSMC has struggled quite a bit with 3nm. N3 is not good, clock regressions and no performance uplift. The only benefit to 3nm is density and power efficiency. N3P and N3X will have to deliver on performance uplift, clock speeds without regression and even better power efficiency.

TSMC make excellent silicon but they are overpriced based on their real world performance. They keep raising silicon prices for their customers and the generation over generation improvements do not justify the cost. Enter Intel 20A and more importantly 18A. Intel has always boasted about their superior silicon density over their competitors. I guess it's a wait and see thing to see what the new 5nm Intel silicon does. I think it's better to call Intel's new stuff 5nm even though they claim it performs much better than 5nm silicon.

If Blackwell was on TSMC 3nm, Nvidia would not have any problems with density and packaging. Nvidia may have other issues outside of the silicon. The Blackwell architecture is big time stuff. That may be the problem, it's a huge leap over the 40 series.

 

[adroc_thurston]

One of Nvidia's problems is the density of the silicon required for Blackwell. N4X is the only TSMC 5nm silicon (TSMC calls it 4nm) that has enough silicon density to accommodate Blackwell's high end offerings well above 5090 GPU's

N4X is power/perf bump, has no additional density.
Either way those are 2.5D issues, not something related to the die itself.

 

[Hitman928]

There are problems at every level - which ones are you calling "2 main issues"?

From your quote:

A major design issue rumored is related to the bridge dies. These bridges need to be redesigned. Also rumored is a redesign of the top few global routing metal layers and bump out of the Blackwell die. This is a primary cause of the multi-month delay.

Then he talks about capacity issues with packaging, which is an obvious issue, but the primary reason for the delay is NV needing to redesign the chips.

 

[ErichZannMusician]

From your quote:



Then he talks about capacity issues with packaging, which is an obvious issue, but the primary reason for the delay is NV needing to redesign the chips.

Read the article. There are issues with reliably placing the intermediate dies as part of the CoWoS-L integration, leading to warpage and potentially affecting the 10 TB/s interconnect between the two GPU dies.

Then there is the capacity issues and the ability to ramp. TSMC needs to convert existing CoWoS-S capacity to CoWoS-L, in order to meet NVIDIA's aggressive ramp targets. They will like fail at that too - causing a 'lumpy' ramp.

 

[Hitman928]

Read the article. There are issues with reliably placing the intermediate dies as part of the CoWoS-L integration, leading to warpage and potentially affecting the 10 TB/s interconnect between the two GPU dies.

Then there is the capacity issues and the ability to ramp. TSMC needs to convert existing CoWoS-S capacity to CoWoS-L, in order to meet NVIDIA's aggressive ramp targets. They will like fail at that too - causing a 'lumpy' ramp.

And yet the primary reason for the delay, is NV design related issues. The rest are just challenges in ramping a new technology at an accelerated pace, which shouldn’t be a surprise to anyone.

 

[ErichZannMusician]

And yet the primary reason for the delay, is NV design related issues. The rest are just challenges in ramping a new technology at an accelerated pace, which shouldn’t be a surprise to anyone.

Is NVIDIA more responsible for the bridge dies and metal bumps, or is it TSMC? It is more complicated than randos on forums conclusively trying to pin the blame on one company or the other.

 

[Hitman928]

Is NVIDIA more responsible for the bridge dies and metal bumps, or is it TSMC? It is more complicated than randos on forums conclusively trying to pin the blame on one company or the other.

NV is responsible for their IC design, not sure why you think that would be TSMC’s responsibility.

 

[Hans Gruber]

N4X is power/perf bump, has no additional density.
Either way those are 2.5D issues, not something related to the die itself.

You are right, my mistake. It's 4NX, that is the Nvidia stuff that has increased density. Sometimes I get confused because the standard N4 stuff is mainstream and Nvidia gets the specialized stuff that no other companies order with inverse node numbers.

 

[ErichZannMusician]

NV is responsible for their IC design, not sure why you think that would be TSMC’s responsibility.

The issue is related to the LSI embedded chiplet in the CoWoS organic substrate which replaces the Si substrate in CoWoS-S. How is it the fault of NVIDIA?

 

[Doug S]

If Nvidia's volume with Blackwell is affected too much they may look to push up the N3 version, since it has exactly what Nvidia needs - more density and reduced power. Clock rates are a tertiary concern for them.

If they are going to be packaging constrained, they might as well be packaging more powerful N3E dies versus N4X dies as soon as it is feasible to do so. Supplies of N3E may still be fairly tight, but a little cash thrown TSMC's way which TSMC can use to bribe other customers with N3E wafer allocations to delay their shipments. Money talks, and Nvidia has plenty of it.

Alternatively, they could use N3E to keep performance constant and reduce power, if the issues with power density are the driver of the delays.

 

[QuickyDuck]

From what I'm hearing, overheating is the culprit

 

[FlameTail]

You are right, my mistake. It's 4NX, that is the Nvidia stuff

Blackwell is 4NP.

Hopper was 4N.

 

[Hitman928]

The issue is related to the LSI embedded chiplet in the CoWoS organic substrate which replaces the Si substrate in CoWoS-S. How is it the fault of NVIDIA?

View attachment 104516

First, he said that there is a design issue in the chips themselves as well as the IC bridge. Second, do you think NV is using a generic off the shelf bridge chip? There's no way, it has to be a custom design specific to Blackwell.