Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[ErichZannMusician]

First, he said that there is a design issue in the chips themselves as well as the IC bridge. Second, do you think NV is using a generic off the shelf bridge chip? There's no way, it has to be a custom design specific to Blackwell.

The bridge "chip" is part of the CoWoS-L implementation.

It's TSMC's IP.

 

[Hitman928]

The bridge "chip" is part of the CoWoS-L implementation.

It's TSMC's IP.

The RDL had to be custom for NV, there’s no way they used a generic TSMC designed bridge. At best, it was co-designed between the two, but I doubt even that is true. If NV didn’t design it entirely themselves, they probably used one of their 3rd party partners to co design it.

 

[ErichZannMusician]

The RDL had to be custom for NV, there’s no way they used a generic TSMC designed bridge. At best, it was co-designed between the two, but I doubt even that is true. If NV didn’t design it entirely themselves, they probably used one of their 3rd party partners to co design it.

And you know all this - how exactly?

 

[maddie]

And you know all this - how exactly?

Intelligence, I assume.

 

[ErichZannMusician]

Intelligence, I assume.

Those with intelligence refrain from assuming things outside of their area of expertise.

 

[maddie]

The bridge "chip" is part of the CoWoS-L implementation.

It's TSMC's IP.

Who has the IP for, say the N3B transistors. TSMC or Nvidia? From your reasoning, TSMC is responsible for any poorly designed chip.

Those with intelligence refrain from assuming things outside of their area of expertise.

Wise advice to follow.

 

[Hitman928]

And you know all this - how exactly?

Experience.

 

[Hitman928]

The base HD cells are 2-1? I thought that was the finflex version with the base HD cell being 2-2.

Yes, 2-1 is Finflex, but by base I meant what their comparison point is. The advertised numbers they gave for density, performance, and efficiency improvement. If you compare 2-2 from N5 family to N3, the numbers are different.

 

[Hitman928]

That last post reminded me that I never followed up on how Finflex works with mixing HD and HP cells. Basically, Finflex allows you to mix HD and HP cells in the same design, giving a HP row for critical timing paths and HD row for paths that can be slower. I'm not talking about a theoretical design where HD cells are used for E-cores and HP cells for P-cores, but rather the P-cores being designed with a mix of HD and HP cells (or HD and UHD cells for E-cores). This is done through a row based approach where, say you are using 3-2, then 1 row of cells is 3 fins cell height, and the next row of cells is 2 fin cell height.

Then any paths requiring high speed go in the top row and lower speed paths go in the bottom row. Since you have to keep the whole row the same height, this probably leads to paths that don't require high speed, still being in the high speed row, just because trying to put only high speed paths in the high speed row isn't practical from a layout perspective, but this will obviously be design dependent. I made a very quick and ugly figure to show what I am trying to describe. The green are the different cells and the blue are the pwr/gnd rails (it will alternate pwr, then gnd, then pwr or vice-versa).

 

[jdubs03]

Well I suppose that’s good news.

Intel Panther Lake has powered on and its on track for 2025 production - VideoCardz.com

Panther Lake on track for 2025 production Intel has achieved a new milestone with its most advanced node that will be used for client and server products. Intel has announced that its leading products on the 18A node, including Panther Lake and Clearwater Forest, have left the fab and...

videocardz.com

 

[DavidC1]

Well I suppose that’s good news.

Intel Panther Lake has powered on and its on track for 2025 production - VideoCardz.com

Panther Lake on track for 2025 production Intel has achieved a new milestone with its most advanced node that will be used for client and server products. Intel has announced that its leading products on the 18A node, including Panther Lake and Clearwater Forest, have left the fab and...

videocardz.com

I hope to see more than just 1 measly customer on 18A soon. Even if we had 5 it would not be amazing. Foundries would need many small and large customers alike. Unless it's something real big like Nvidia bringing most of Blackwell on 18A.

Intel already has a Foundry win on Ericsson and that's on Intel 4. We know they are continuing their partnership.

To see a real push towards Intel Foundry, their has to be a huge advantage of moving to it.

Theoreticals:
-Say you are a customer on TSMC.
-Intel on 18A offers EXACTLY the same tools as TSMC
-18A is better as Intel claims

Having same tools makes it easier/cheaper to move to Intel, but why would you move to Intel? Because they are a little better? You want to risk your business on a foundry that basically just started and has no experience, a company that's historically known to drop projects on a whim, and recently just had terrible financial news? Some will not move on a small gain purely because they don't feel like it. Moving on a technical advantage like transistor performance needs massive advantage.

The real reason Intel Foundry growth will be slow is because of CONFIDENCE. Confidence is built over years and years of stable execution. TSMC has foundry advantage over Intel like Intel has over AMD. You need to break the mindset decisively and for many years. Some like big finance won't move from Intel for a while. Same with TSMC to Intel, assuming Intel has a noticeable foundry lead.

 

[NostaSeronx]

GlobalFoundries plans to restart 3D-stacking ambitions starting with 22FDX at Malta.

2025? -- Malta (internally) = up to 5-level stacking = up to 5-die stack
2027? -- Malta and Dresden (externally via external 3DS/3DIC partner) = up to 25-level stacking = up to 25-die stack

Current status for FinFET is only up to 3-level stacking which has yet to go mass production. So far, the assumption is that it will never go mass production.

Of which, the 22FDX appears to already have a mostly homogeneous design set for mass production.
4 dies of InO 64-bit cores.
1 die of L3, I/O, misc.
The above is filed either in "Datacenter" => Datacenter AI or under "IoT" => Edge IoT AI.

But is actually filed under "The Compute, Control and AI Business Line targets a broad set of applications ranging from video surveillance, audio processing, human interfaces, motor control, building automation etc… Customers are focused on maximizing the compute performance they can extract from their implementations thanks to adoption of enhanced features such as advanced body-biasing, fast memory accesses and optimized design techniques, all within a limited power budget."

 

[oak8292]

Intel really needs to find some trailing customers through their partnership with UMC. They really need to fill the fabs in Arizona that they will be moving out of. Having a customer on leading edge is a great concept but based on their desire to have technical advantages across the board it is really asking a lot.

I have the impression with both 4 nm and 20A that these slightly less dense nodes exclusively focused on tall transistors for CPUs are not offered to customers to keep a frequency advantage for Intel. Intel has relaxed the geometry on both 14 and 10 to achieve the higher frequencies they need for desktops. There is a power disadvantage which doesn’t matter to gamers. Intel marketing is still all about ‘performance’ for the top end chip no matter how the rest of the portfolio is performing.

 

[misuspita]

Oops, wrong thread

 

[FlameTail]

Note the die size reduction from 8 Gen 1 to 8+ Gen 1.

They are both the same SoCs. 8 Gen 1 is on Samsung 4LPX, and 8+ Gen 1 is on TSMC N4.

This means N4 is a whopping 25% denser than 4LPX.

 

[LightningZ71]

"Practical density" N4 probably can retain performance at the limits of its density better than 4LPX.

 

[SiliconFly]

I have the impression with both 4 nm and 20A that these slightly less dense nodes exclusively focused on tall transistors for CPUs are not offered to customers to keep a frequency advantage for Intel.

Not really. Intel 3 & 18A offer a revised version of the same *tall transistors* for all customers.

 

[oak8292]

Not really. Intel 3 & 18A offer a revised version of the same *tall transistors* for all customers.

There are slight revisions between ‘tall transistors’ in 14 nm and 10 nm with ‘relaxed’ geometries and other changes that increased the max. frequency.

 

[SiliconFly]

There are slight revisions between ‘tall transistors’ in 14 nm and 10 nm with ‘relaxed’ geometries and other changes that increased the max. frequency.

Yep. Intel was into UHP cells way too much with 14, 10 (both original 10 and revised 10 -> 7). With 7, the density was slightly more 'relaxed' giving the products insane frequencies, bad thermals, extreme power draw & all the issues related to the recent recall & bios/µcode patches. Thank god it's over.

Intel 4 & 20A are primarily HP libraries only. But, Intel 3 & 18A have a wider range of libraries for everyone including the ones in Intel 4 & 20A. So, no one's left out.

 

[oak8292]

Yep. Intel was into UHP cells way too much with 14, 10 (both original 10 and revised 10 -> 7). With 7, the density was slightly more 'relaxed' giving the products insane frequencies, bad thermals, extreme power draw & all the issues related to the recent recall & bios/µcode patches. Thank god it's over.

Intel 4 & 20A are primarily HP libraries only. But, Intel 3 & 18A have a wider range of libraries for everyone including the ones in Intel 4 & 20A. So, no one's left out.

I’ll take your word for it that it is over but I wouldn’t be surprised if it isn’t. What will it take to sell a K processor. Bin it till you win it.

 

[SiliconFly]

I’ll take your word for it that it is over but I wouldn’t be surprised if it isn’t. What will it take to sell a K processor. Bin it till you win it.

We can only hope that by now they've learnt extreme high frequencies is not the only answer for higher performance.

 

[poke01]

Sina Visitor System

TSMC buys High NA EUV fab

 

[oak8292]

View attachment 105073

Sina Visitor System

TSMC buys High NA EUV fab

I don’t think this is real or I am mis-understanding something. In a quarterly conference call in April of 2022 ASML said;

Roger Dassen

“…So, I will try and give you a non-answer to your question on the High-NA orders, Adi. So, we did disclose that we have 5 orders for High-NA 5000, for the 5000 system. That's an R&D system. We've also indicated we have multiple orders for the 5200, and we've also said that we have these orders from three logic customers and two memory customers, and that's really what we can share…”

This would lead me to believe that TSMC had an order in on a development NA-EUV machine since 2022 as they are one of three logic customers. I seen a rumor is that ASML already starting sending TSMC their 5000 development machine.

This is inference and rumor on my part as there is nothing explicitly said by ASML but as a betting man I don’t think TSMC is waiting for ASML to lower the price.

 

[H433x0n]

First good news out of Intel in a while.

In the Deutsche bank conference today we got our first real numbers on how Intel’s new processes are yielding.

Excerpt below:

We described that as our five nodes in the four-year journey and we see the finish line in the site. And since we released the fifth of those, right, the PDK for Intel 18A, we've seen a market uptick in activities in the industry. We now have about a dozen customers that are actively engaged with us around that PDK. We have eight product tape-ins that we expect to finish by the middle of next year. And of course, Panther Lake and Clearwater Forest, our first client and server product. And I'm happy to update the audience that we're now for this as a production process, we're now below 0.4 D0 as defect density.

I’m guessing he gave hard numbers on defect density in response to Stacy Rasgon and the report in Digitimes. That’s not a bad defect density for this stage in development, that’s actually pretty good considering how complex 18A is.

 

[DavidC1]

I’m guessing he gave hard numbers on defect density in response to Stacy Rasgon and the report in Digitimes. That’s not a bad defect density for this stage in development, that’s actually pretty good considering how complex 18A is.

Ok, I guess but they'll need to execute their plans nearly perfectly to have any chance.