Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[igor_kavinski]

You can get the performance you need out of the xtor by building it taller (Z),

Nothing comes for free. Building it taller may amplify some other undesirable characteristic of the transistor.

 

[maddie]

Nothing comes for free. Building it taller may amplify some other undesirable characteristic of the transistor.

Not quite what you meant, but adding each layer of ribbon means that all the fab steps needed for the 1st ribbon has to be repeated, and these levels are the densest needing EUV machines. Finfets could do N# fins in one pass, Ribonfet can't. This will reduce output and raise costs significantly. We're going to see some interesting design tradeoffs.

 

[NostaSeronx]

Just food for thought, TSMC might stack nanosheets upside-down.


Instead of having increased height, TSMC might instead opt for increasing depth.
(Origin-reference: IBM's (now GlobalFoundries; GlobalFoundries vs TSMC dispute made it TSMCs) Upside-down FETs:
)

Post-2nm might be interesting.

 

[igor_kavinski]

adding each layer of ribbon means that all the fab steps needed for the 1st ribbon has to be repeated, and these levels are the densest needing EUV machines. Finfets could do N# fins in one pass, Ribonfet can't.

Is it possible they might reserve the products requiring the most layers for the high end, like the x900K series? That way, they can offset the additional expense by simply charging more for increased performance.

 

[maddie]

Is it possible they might reserve the products requiring the most layers for the high end, like the x900K series? That way, they can offset the additional expense by simply charging more for increased performance.

Sure, however, the issue with that is effectively a different core design with it's unique design costs for each ix/Rx core. Costs increase all around as even the simpler (less ribbons) designs now have less sales to amortize fixed R&D costs.

Defects also increase with more ribbon layers. Design engineers are going to be busy.

 

[igor_kavinski]

https://twitter.com/x/status/1539994595769176064

Goldmine of a thread. Really explains why Intel is stuck in the past. As one guy there says, "Intel refused to listen to or respect outside experience". The old guard there is gonna take the whole ship down if they don't open their minds and embrace change ASAP.

 

[ashFTW]

So, doesn’t that improve density? You can get the performance you need out of the xtor by building it taller (Z), rather than adding more fins in the XY dimension.

Compared to FinFet, GAA absolutely will improves density. And back side power delivery being implemented alongside, should also help.

What I was pointing out is that with GAA, if “nanosheetFlex” is implemented, the different transistor types with varying number of nanosheets will all occupy the same area. With FinFlex different transister types have different density on the same FinFet chip.

 

[Doug S]

Compared to FinFet, GAA absolutely will improves density. And back side power delivery being implemented alongside, should also help.

What I was pointing out is that with GAA, if “nanosheetFlex” is implemented, the different transistor types with varying number of nanosheets will all occupy the same area. With FinFlex different transister types have different density on the same FinFet chip.

Finflex can be used to allow inserting high performance transistors in an otherwise power efficient transistor circuit to speed up a critical path, or alternatively to insert power efficient transistors in an otherwise high performance transistor circuit off the critical path to reduce power consumption.

Those goals are just as important even if high performance and power efficient transistors require the same area in the GAA era. Perhaps more important, because we're only a few generations away from the first trillion transistor chip.

I could see timing closure calculations doing this automatically. Why waste power in parts of a circuit that have timing margin to spare? Likewise if you can get another hundred MHz by sprinkling a few high performance transistors around a mobile core in areas hitting the critical timing path, why not?

 

[Ajay]

Compared to FinFet, GAA absolutely will improves density. And back side power delivery being implemented alongside, should also help.

What I was pointing out is that with GAA, if “nanosheetFlex” is implemented, the different transistor types with varying number of nanosheets will all occupy the same area. With FinFlex different transister types have different density on the same FinFet chip.

Thanks for clarifying.

 

[Ajay]

With the CHIPS act looking DOA:

Intel Puts Ohio Fab Groundbreaking Ceremony on Hold, Indefinitely

The US Congress hasn't been able to agree on passing what is known as the CHIPS Act, which consists of some US$52 billion in subsidies for semiconductor manufacturers and it appears that Intel isn't very pleased. As such, the company is said to have put the brakes on the groundbreaking ceremony...

www.techpowerup.com

 

[JasonLD]

With the CHIPS act looking DOA:

Intel Puts Ohio Fab Groundbreaking Ceremony on Hold, Indefinitely

The US Congress hasn't been able to agree on passing what is known as the CHIPS Act, which consists of some US$52 billion in subsidies for semiconductor manufacturers and it appears that Intel isn't very pleased. As such, the company is said to have put the brakes on the groundbreaking ceremony...

www.techpowerup.com

Intel doesn't exactly need Ohio fab in desperate fashion when they are building 2 new fabs in Arizona and Germany respectively.

 

[Doug S]

With the CHIPS act looking DOA:

Intel Puts Ohio Fab Groundbreaking Ceremony on Hold, Indefinitely

The US Congress hasn't been able to agree on passing what is known as the CHIPS Act, which consists of some US$52 billion in subsidies for semiconductor manufacturers and it appears that Intel isn't very pleased. As such, the company is said to have put the brakes on the groundbreaking ceremony...

www.techpowerup.com

They only put the groundbreaking ceremony on hold, they haven't announced any change as far as the start of construction (which is still set for the end of the year)

Maybe Intel doesn't want to give politicians a photo op without having something delivered first. And maybe the politicians wouldn't want to show up without that either - they don't want to give opponents ammunition looking foolish bragging about something that doesn't happen (i.e. Foxconn plant in Wisconsin)

 

[pakotlar]

They only put the groundbreaking ceremony on hold, they haven't announced any change as far as the start of construction (which is still set for the end of the year)

Maybe Intel doesn't want to give politicians a photo op without having something delivered first. And maybe the politicians wouldn't want to show up without that either - they don't want to give opponents ammunition looking foolish bragging about something that doesn't happen (i.e. Foxconn plant in Wisconsin)

Yeah they're putting on some political pressure. The need for Western manufacturing is real, and Intel appears to me to be saying that if the US won’t invest there will be consequences (right as they receive a $7B commitment from Germany for a $17B fab).

 

[szrpx]

The TRUTH of TSMC 5nm

Claimed Density vs Reality

www.angstronomics.com

You must post your personal commentary to all links and images. This is your one zero point warning


esquared
Anandtech Forum Director

 

[Henry swagger]

The TRUTH of TSMC 5nm

Claimed Density vs Reality

www.angstronomics.com

Why would TSMC cite theoretical density, if they are actually producing significantly less dense chips?', and the answer is simple, they want investors and clients to believe they are further ahead of the competition (Intel, Samsung) ... grreat article exposing tge marketing of these foundries 😏

 

[DrMrLordX]

Why would anyone be complaining about the transistor density of N5 now? Several companies have already made use of N5 for years with successful product launches. Wafers from N5 and variants are highly-sought-after by designers. Even Intel has ordered N5 and N4 wafers. Nobody who is designing chips has any illusions about what they can and can not achieve on that node.

 

[Henry swagger]

Why would anyone be complaining about the transistor density of N5 now? Several companies have already made use of N5 for years with successful product launches. Wafers from N5 and variants are highly-sought-after by designers. Even Intel has ordered N5 and N4 wafers. Nobody who is designing chips has any illusions about what they can and can not achieve on that node.

He's just exposing marketing lies.. we need full transparency from companies

 

[moinmoin]

Yellow press style click baiting... so that's the direction of Angstronomics.

@Henry swagger guess what other company keeps quoting high density (despite repeatedly and increasingly coming a cropper with those for over a decade now) while launching chips on successively relaxed densities?

 

[DrMrLordX]

we need full transparency from companies

All of them? Or just TSMC?

 

[Henry swagger]

All of them? Or just TSMC?

All of them ✅

 

[Ajay]

He's just exposing marketing lies.. we need full transparency from companies

Technically, we don’t. And like @DrMrLordX pointed out, the design engineers know the real deal once the go over the PDK and RDL limitations.

 

[Doug S]

Technically, we don’t. And like @DrMrLordX pointed out, the design engineers know the real deal once the go over the PDK and RDL limitations.

Yes, it is silly for us to be worried about this. TSMC isn't "marketing" N5 and Intel isn't marketing Intel 4 towards consumers, even the biggest enthusiast consumers. They will quote the most optimistic numbers they can during presentations but we aren't the audience. Wall Street (and whatever Taiwan's Wall Street is called) is.

Those numbers are undoubtedly true, under a given set of assumptions. How close those assumptions are to actual designs is a different matter, but as you say the design engineers know the real numbers for their design so no one is being fooled other than keyboard warriors who for some reason want to pimp for or against particular fabs.

The Angstronomics site doesn't exactly have a long track record (it started about a month ago from what I can tell) but the name chosen for it may indicate a certain bias towards Intel. The article on TSMC N5 sure seems like a "TSMC sucks, go Intel" agenda is being pushed, we'll have to see how they handle Intel when articles with them as the subject are written.

 

[Markfw]

All of them ✅

Intel is the worst in this area. I have not seen anything approaching real transparency in so many years, I can't count.

 

[jpiniero]

They only put the groundbreaking ceremony on hold, they haven't announced any change as far as the start of construction (which is still set for the end of the year)

Cant see Intel doing any fabs without subsidies. They would have to have the confidence that 7 nm and any other future node won't take 5 years to get to decent yield.

 

[moinmoin]

Cant see Intel doing any fabs without subsidies. They would have to have the confidence that 7 nm and any other future node won't take 5 years to get to decent yield.

Ouch!