Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[invisible_city]

18A is 2nd gen GAAFET & 2nd gen BSPD. They've had enough time to work out the issues. 18A shouldn't face any major problems (like 20A's probably limited supply; something I expect).


Too soon if you ask me.


Thats because Intel's trying to turn the ship around. But they're not there yet. And the future can be either: Moonshot or Titanic. I don't think we should discuss money matters here, but my advice is, be cautious. Even though I like him a lot, Pat's words shouldn't be taken literally. Who knows what all skeletons Intel still has in its closet.

Timing the market is impossible. I bought Nvidia and AMD in 2012. No one thought that was a good idea at the time. Intel is at an insanely low price relative to future earnings if they execute on chips and fabs. To be seen if that pans out, but you can’t get 10x+ returns by buying when it’s obvious.

 

[SiliconFly]

Timing the market is impossible. I bought Nvidia and AMD in 2012. No one thought that was a good idea at the time. Intel is at an insanely low price relative to future earnings if they execute on chips and fabs. To be seen if that pans out, but you can’t get 10x+ returns by buying when it’s obvious.

I agree. More the risk, more the reward. But it can go either way. And an investor should be ready for both! Thats all I'm saying.

 

[FlameTail]

https://twitter.com/x/status/1800347787617583222

TSMC’s 3nm process production lines are booked through 2026 by 4 major clients, Apple, Qualcomm, Nvidia and AMD, media report, noting smartphones and AI servers/ HPC (high performance computing) are the main end products. TSMC 3nm capacity has already expanded 3x this year, but it’s not enough, so TSMC has converted some 5nm production lines to 3nm, which may increase 3nm capacity to 180,000 wafers-per-month from 120,000 now.

As expected. That "converting 5nm production line to 3nm" is interesting though. I didn't know that was possible.

 

[Doug S]

https://twitter.com/x/status/1800347787617583222

As expected. That "converting 5nm production line to 3nm" is interesting though. I didn't know that was possible.

It is all the same equipment, the difference between N5 and N3 is in how the wafers are moved around the fab to the different stations and how long the whole process takes (due to how many stops are made at each station) They should have the same ability to switch from N3 to N2 when the time comes, but maybe not with A16 since BSPDN will require some new equipment/stations. Though I suppose if they had it in mind to allow that flexibility they could reserve space when they build out N3 or N2 lines to insure sufficient room exists to install the new equipment when they convert to A16. Obviously there will be a hard line in the sand when they adopt high-NA, which seems like it will be with A10.

They would have to be seeing a big drop in the amount of N5 family demand to be able to move so much capacity to N3. Obviously Apple's N5 wafer starts are way down, and Qualcomm is moving their high end to N3 but isn't their volume in low/mid range stuff? Or is their midrange moving to N3 as well? Isn't Nvidia still all N5 family? Isn't AMD? Those latter if anything want more N5 wafers, not less, and AFAIK won't need N3 until next year.

Seems unlikely they could pull that much off of N5 when Apple and to a lesser extent Qualcomm are the only companies reducing their demand for N5, while Nvidia and AMD are if anything increasing it (Nvidia seems to be limited by packaging though so maybe they aren't increasing their wafer demand all that much)

Maybe the dark wafers not as readily reported being purchased by hyperscalers like Amazon and Microsoft are silently moving from N5 to N3?

 

[igor_kavinski]

Timing the market is impossible.

Watch the Veritasium video on that (I think this one:

). Apparently there are hedge funds who have mastered the art through some complex algorithms.

 

[invisible_city]

Watch the Veritasium video on that (I think this one:

). Apparently there are hedge funds who have mastered the art through some complex algorithms.

Yeah, afaik those guys tend to try to find intraday correlations. Those movements do exist. I just mean the long run average is approximately a random walk.

Thanks for the video, will watch!

 

[desrever]

Watch the Veritasium video on that (I think this one:

). Apparently there are hedge funds who have mastered the art through some complex algorithms.

This is 50 years ago and won't work today. Today's successful trading funds are using much more complicating trading strategies. Most hedge funds actually don't even out perform the market even with all their math and data.

 

[deasd]

N3 is in tight supply, 25% more expensive than N5

https://twitter.com/x/status/1801074525502935342

 

[FlameTail]

Imagine what will happen when N2 lands. N3 -> N2 is said to be a 50% cost increase, far bigger than the 25% of N5 -> N3.

 

[LightningZ71]

I have to think that we're going to be stacking N2 class logic chips on top of N5/N4 class cache chips soon. The extra cost and product loss due to failed bonding will be FAR outweighed by the gains from shrinking the logic chips on leading edge process tech down to their smallest possible sizes. I say N5/N4 class for the cache chip because it is reported that N3B barely shrank cache cells and N3E backed off to N5/N4 density cells for yield/cost reasons. BSPD may enable shrinking cache a bit more, but at what cost and for what gain?

Looking forwards, I can see a need for a product that has several chips stacked...

High Performance CCD (leading edge node - performance optimized process)
| | | | | | | |
L3 Cache and logic to connect to I/O chip (trailing node for L3 cache optimization)
| | | | | | | | | | | | | | | | |
dense LP cores | | | | | | | | | (leading edge node - efficiency optimized process)
X X X X X X X X | | | | | | | | |
I/O Logic + minimal display engine (N-2 or more trailing node)

Maybe that's too much, but, it seems where it needs to go.

 

[FlameTail]

We'll need a massive expansion of advanced 3D packaging capacity then. Currently, all the capacity is taken up by AI/Server chips.

 

[Aapje]

Production capacity shortages are temporary. The companies will scale up to meet (expected) demand.

 

[Ajay]

N3 is in tight supply, 25% more expensive than N5

https://twitter.com/x/status/1801074525502935342

Wait, what?? That’s the wholesale price?

 

[Doug S]

Surprised that no one has mentioned ASML's pre-announcement that they're working on hyper-NA to follow high-NA, looking at aperatures of .75 to .85, targeting early next decade.

https://www.eetimes.com/asml-aims-for-hyper-na-euv-shrinking-chip-limits/

 

[Ajay]

Dang. Wonder what the reticle sizes will be.

 

[biostud]

New packaging technology from Samsung

Revolutionary Samsung tech that enables stacking HBM memory on CPU or GPU arrives this year — SAINT-D HBM scheduled for 2024 rollout, says report

Tech to debut ahead of HBM4 (2025/26)

www.tomshardware.com

 

[Curious_Inquirer]

There’s a rumor by Ming Chi Kuo that the Exynos 2500 has been cancelled due to low yields. Frankly terrible news for their foundry given they’re trying to get it off the ground.

https://twitter.com/x/status/1802737528874955169

Edit: At this point TSMC has a complete monopoly on smartphone SOC’s

 

[igor_kavinski]

New packaging technology from Samsung

Revolutionary Samsung tech that enables stacking HBM memory on CPU or GPU arrives this year — SAINT-D HBM scheduled for 2024 rollout, says report

Tech to debut ahead of HBM4 (2025/26)

www.tomshardware.com

Could the 3D SRAM be why AMD is using them for one of their future products?

 

[Curious_Inquirer]

Could the 3D SRAM be why AMD is using them for one of their future products?

AMD’s 3D V-Cache is their entire project with TSMC. As far as I know the only collaboration with Samsung is with their HBM on their MI300A/X products and PIM(Processing In Memory) on their Xilinx Versal Products.

 

[LightningZ71]

There's apparently strong rumors that AMD's next budger line chip will be a samsung product. I hope that it's on an already established node.

 

[FlameTail]

Is Semiaccurate implying that Nvidia's ARM PC SoC will be made at Intel Foundry?

All of these changes are interesting but the most important is probably ARM’s increased offerings of CPU and GPU physical designs. This time around TSMC 3nm is the target but if Intel’s Foundry conference attendance and speaker list was any indication, don’t be surprised to see Intel 3/18a implementations too. *COUGH*. No clue who though, really.

ARM Outs Their New IP lineup for 2024

Last week ARM unveiled their new IP that will be featured in the devices consumers buy in 2025.

semiaccurate.com

 

[DrMrLordX]

There’s a rumor by Ming Chi Kuo that the Exynos 2500 has been cancelled due to low yields. Frankly terrible news for their foundry given they’re trying to get it off the ground.

https://twitter.com/x/status/1802737528874955169

Edit: At this point TSMC has a complete monopoly on smartphone SOC’s

Just for clarity, but would that be the 3GAP node which is now . . . SF3 I think?

 

[biostud]

There's apparently strong rumors that AMD's next budger line chip will be a samsung product. I hope that it's on an already established node.

I wouldn't mind if there were some competition in the GPU market on price/performance. If AMD could have 20%+ better price/performance in the sub $999 market that would be really nice.

 

[FlameTail]

Just for clarity, but would that be the 3GAP node which is now . . . SF3 I think?

Yes

 

[lightisgood]

TSMC N3E has been analyzed by TechInsights.
As like you had known, there are SRAM density regression and logic density regression (c.f. N3B)...