Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[A///]

There is also an N4X node:

TSMC Unveils N4X Node: Extreme High-Performance at High Voltages

www.anandtech.com

is anyone using these?

 

[DrMrLordX]

is anyone using these?

Wish I knew. Wouldn't surprise me if a POWER variant wound up on this node (assuming IBM even bothers).

 

[qmech]

TSMC N4 is a rebranded N5?

No. N4 is a member of the "N5 family", but is not identical. Among other things, N4 features more EUV layers to reduce multi-patterning and mask use, some BEOL changes, and some standard cell adjustments (which, if used, would enable a (very) small increase in density)

Similar to how TSMC pushed its N7 clients to N6, N4 is the preferred "N5 family" process, with a slightly better combination of costs, throughput, and effective yield. This would seem to be corroborated by the reporting from Tech Insights.

 

[A///]

Wish I knew. Wouldn't surprise me if a POWER variant wound up on this node (assuming IBM even bothers).

I read parts of it when it came out but I thought IBM have come up with ehri hour own 2nm process which samsung would fab through their partnershi p announced a few years ago and not tsmc which would be a ste back to for them.

 

[H433x0n]

VLSI Japan: It’s Better on the Backside

Intel announces its PowerVia technology, and scaling the backside is the next big thing. This could be Intel's moment.

www.fabricatedknowledge.com

Article from somebody who attended VLSI and covers the industry.

IMO, it’s already over and TSMC lost process leadership for HPC. We’re not seeing it yet since the products haven’t released but they will begin trickling out in the next 12 months. I look forward to being mocked over this statement. Does this forum have a “RemindMe” bot?

 

[FlameTail]

VLSI Japan: It’s Better on the Backside

Intel announces its PowerVia technology, and scaling the backside is the next big thing. This could be Intel's moment.

www.fabricatedknowledge.com

Article from somebody who attended VLSI and covers the industry.

IMO, it’s already over and TSMC lost process leadership for HPC. We’re not seeing it yet since the products haven’t released but they will begin trickling out in the next 12 months. I look forward to being mocked over this statement. Does this forum have a “RemindMe” bot?

So you say Intel is the process leader?

 

[H433x0n]

So you say Intel is the process leader?

In the HPC segment, I would say so. I'm going to caveat it with the following:

This doesn't mean I think IFS is going to be the worlds #1 fab or come close to TSMC market share. I think TSMC will remain the top fab by volume for the foreseeable future. I would say IFS would be fortunate if they hit 20% of TSMC's volume. TSMC will also still retain leadership with certain segments - mainly low power mobile. I think the competition for high performance computing is already over though.

 

[moinmoin]

IMO, it’s already over and TSMC lost process leadership for HPC.

So you say Intel is process leader in backside power delivery? What concrete parameters of silicon quality affects that? And why would that only matter in HPC?

Edit: Having read the article, the author himself refers to EUV as a comparison point recalling that TSMC had EUV back in 2016 while Intel finally got it working in Intel 4 this year. And Intel wants BSPDN working next year while TSMC plans to have it in 2026. Let's see how this timeline turns out.

 

[Doug S]

So you say Intel is process leader in backside power delivery? What concrete parameters of silicon quality affects that? And why would that only matter in HPC?

Edit: Having read the article, the author himself refers to EUV as a comparison point recalling that TSMC had EUV back in 2016 while Intel finally got it working in Intel 4 this year. And Intel wants BSPDN working next year while TSMC plans to have it in 2026. Let's see how this timeline turns out.

Intel implements on a different schedule. They used copper before TSMC did, they used FinFET before they did. They used SAC years ago and TSMC still doesn't - it is kind of amazing they have not needed it. Apparently with N3 they did SAC but they dropped it again with N3E. They may have finally reached gate dimensions where it will become necessary for them.

Intel may get BPD in advance but AFAIK they have nothing like FinFlex, and we will have to see how much that benefits the N3 generation especially in the second iteration (N3P/N3S) after customers have figured out how best to use it.

 

[Ajay]

In the HPC segment, I would say so. I'm going to caveat it with the following:

This doesn't mean I think IFS is going to be the worlds #1 fab or come close to TSMC market share. I think TSMC will remain the top fab by volume for the foreseeable future. I would say IFS would be fortunate if they hit 20% of TSMC's volume. TSMC will also still retain leadership with certain segments - mainly low power mobile. I think the competition for high performance computing is already over though.

LOL! Could have said that 10 years ago and would have been wrong. Maybe Intel gets back on top if they execute 100% on plan - that'll just mean they are able to compete for some sales. Most HPC products will probably still come from TSMC, because their volume is just huge. To be able to scale that high - Intel needs a process which handles more than just HPC. That's the problem - volume becomes the dominant factor in node development, as we saw on TSMC's side with the billions of small phone SoCs helping them to rise to the top.

 

[moinmoin]

Intel implements on a different schedule.

Oh sure, I'm not saying Intel, TSMC or any other foundry must follow a specific adamant sequence. The comparison with EUV is just kind of funny since Intel clearly didn't voluntarily decide to wait that long with using EUV.

 

[H433x0n]

LOL! Could have said that 10 years ago and would have been wrong. Maybe Intel gets back on top if they execute 100% on plan - that'll just mean they are able to compete for some sales. Most HPC products will probably still come from TSMC, because their volume is just huge. To be able to scale that high - Intel needs a process which handles more than just HPC. That's the problem - volume becomes the dominant factor in node development, as we saw on TSMC's side with the billions of small phone SoCs helping them to rise to the top.

10 years ago that would’ve been an objectively correct statement since Intel was ahead of TSMC & Samsung in 2013. They had a multi year lead over TSMC when they first rolled out 14nm. I would say the situation is analogous to RibbonFet & PowerVia now.

 

[DisEnchantment]

TSMC in rearview mirror.

 

[Doug S]

Oh sure, I'm not saying Intel, TSMC or any other foundry must follow a specific adamant sequence. The comparison with EUV is just kind of funny since Intel clearly didn't voluntarily decide to wait that long with using EUV.

Intel had always said that 7nm (what they now call Intel 4) was where they would use EUV. The problem is that they figured they'd rolling out 7nm in 2018/2019 if they had followed their roadmaps from 10 years ago. Instead they were stuck on 10nm until about five minutes ago.

So yeah, they didn't voluntarily wait that long to begin using EUV, but they did start using it on the node they said they would.

 

[Exist50]

People fixate too much on headline-grabbing features. Yeah, stuff like backside PD, GAAFET, EUV, etc matter, but they're not the end all be all. Intel says, for example, PowerVia provides 6% better performance at Fmax (i.e. high-V). That's nice and all, but 6% is very comparable to incremental refinements between nodes. For example, N4 -> N4P also netted 6%, by TSMC's numbers, and that was an already mature technology. Also, high-V is the least useful design point for most customers. Server, mobile, graphics, etc are all low to mid V.

Features like GAAFET and backside PD can help Intel be competitive, but they are neither sufficient in their own right nor likely to cause Intel to "blow past" TSMC. And that's under the big assumption they deliver on time.

 

[Ajay]

People fixate too much on headline-grabbing features. Yeah, stuff like backside PD, GAAFET, EUV, etc matter, but they're not the end all be all. Intel says, for example, PowerVia provides 6% better performance at Fmax (i.e. high-V). That's nice and all, but 6% is very comparable to incremental refinements between nodes. For example, N4 -> N4P also netted 6%, by TSMC's numbers, and that was an already mature technology. Also, high-V is the least useful design point for most customers. Server, mobile, graphics, etc are all low to mid V.

Features like GAAFET and backside PD can help Intel be competitive, but they are neither sufficient in their own right nor likely to cause Intel to "blow past" TSMC. And that's under the big assumption they deliver on time.

100% on the bolded text. On time, good yields, targeted parametrics and density. Then they get ~ 2 years on TSMC (who won't be sitting still either). IIRC, 18A is the target node for IFS, which I consider essential to Intel's success going forward. That's the one that really has to deliver above all. IMHO.

 

[H433x0n]

There's this underlying assumption that TSMC is infallible, whereas the execution the past 3 years proves that to be false. The release of N3 is a year (or more) behind schedule. If you consider N3B to be a part of the N3 family, then technically it's only 6-7 months behind schedule but I would argue N3B isn't a real product. N3B missed almost every metric it was supposed to hit when you look at the numbers. It uses 80% more layers, provides a 5% sram shrink and a total node shrink of 30% with yield issues. The IP for N3B also can't be ported to other N3 variants making it essentially unusable for everybody but Apple (even that's debatable if Apple will use it). It's basically a node for PR and investor relations that was only announced as 'ready' for volume production on December 29th which is literally in the last day(s) of Q4 2022. N3B is a regression in costs per transistor with N3E providing at best a flat cost per transistor upgrade over N5 (35% more expensive for 18% to 39% more density for 2-3 and 2-2 variant respectively.

Edit: I searched everywhere, and I could not find a product released on TSMC N3. At this rate, MTL will be out before there is a product on TSMC N3 (Unless Apple is releasing the iPhone 15 in August / September).

People fixate too much on headline-grabbing features. Yeah, stuff like backside PD, GAAFET, EUV, etc matter, but they're not the end all be all. Intel says, for example, PowerVia provides 6% better performance at Fmax (i.e. high-V). That's nice and all, but 6% is very comparable to incremental refinements between nodes. For example, N4 -> N4P also netted 6%, by TSMC's numbers, and that was an already mature technology. Also, high-V is the least useful design point for most customers. Server, mobile, graphics, etc are all low to mid V.

Features like GAAFET and backside PD can help Intel be competitive, but they are neither sufficient in their own right nor likely to cause Intel to "blow past" TSMC. And that's under the big assumption they deliver on time.

BPD is just a means of “unlocking” future density increases, the marginal increase in fmax is an added perk.

 

[maddie]

There's this underlying assumption that TSMC is infallible, whereas the execution the past 3 years proves that to be false. The release of N3 is a year (or more) behind schedule. If you consider N3B to be a part of the N3 family, then technically it's only 6-7 months behind schedule but I would argue N3B isn't a real product. N3B missed almost every metric it was supposed to hit when you look at the numbers. It uses 80% more layers, provides a 5% sram shrink and a total node shrink of 30% with yield issues. The IP for N3B also can't be ported to other N3 variants making it essentially unusable for everybody but Apple (even that's debatable if Apple will use it). It's basically a node for PR and investor relations that was only announced as 'ready' for volume production on December 29th which is literally in the last day(s) of Q4 2022. N3B is a regression in costs per transistor with N3E providing at best a flat cost per transistor upgrade over N5 (35% more expensive for 18% to 39% more density for 2-3 and 2-2 variant respectively.

Edit: I searched everywhere, and I could not find a product released on TSMC N3. At this rate, MTL will be out before there is a product on TSMC N3 (Unless Apple is releasing the iPhone 15 in August / September).


BPD is just a means of “unlocking” future density increases, the marginal increase in fmax is an added perk.

The trouble with your reasoning is it appears you're implying that Intel will have some superior exclusive tech going forward. IF they execute, this will give them a temporary gain, but in their capacity + other factors are so far behind, that they probably won't get any revolutionary gain with this. They will have to repeat this sort of jump many times before they can think of leading once more.

 

[H433x0n]

The trouble with your reasoning is it appears you're implying that Intel will have some superior exclusive tech going forward. IF they execute, this will give them a temporary gain, but in their capacity + other factors are so far behind, that they probably won't get any revolutionary gain with this. They will have to repeat this sort of jump many times before they can think of leading once more.

It’s not exclusive, everybody will eventually adopt BPD. You're assuming TSMC is far ahead and that was true for 2021 but here we are halfway through 2023 and there are no products with TSMC N3 silicon. The first proper N3 node (N3E) will not be in products until Q2 2024.

 

[maddie]

It’s not exclusive, everybody will eventually adopt BPD. You're assuming TSMC is far ahead and that was true for 2021 but here we are halfway through 2023 and there are no products with TSMC N3 silicon. The first proper N3 node (N3E) will not be in products until Q2 2024.

Didn't you write this, "IMO, it’s already over and TSMC lost process leadership for HPC" concerning BSP? As a comparison, could a person have claimed the same in reverse when TSMC adopted EUV many years before Intel, and yet, here we are. In fact, EUV and its successor is more fundamental to advancement than BSP will be. You literally can't make transistors below a certain dimension without it, but you can without BSP. I'm NOT saying its not important, but no there's magic here, only the normal to & fro. As I wrote, Intel needs to do this sort of thing repeatedly for years to return to leadership.

 

[H433x0n]

Didn't you write this, "IMO, it’s already over and TSMC lost process leadership for HPC" concerning BSP? As a comparison, could a person have claimed the same in reverse when TSMC adopted EUV many years before Intel, and yet, here we are.

Yes, it would've been accurate to say TSMC firmly took process leadership back in ~2017 / 2018. This would have been ~1 year before N7 (and then N7+) became commercially available. By that timeframe, it was essentially already over for both Samsung and Intel.

I'm NOT saying its not important, but no there's magic here, only the normal to & fro. As I wrote, Intel needs to do this sort of thing repeatedly for years to return to leadership.

They could miss their stated deadline by 6 months and still be ahead by more than a year. TSMC N2P is not going to be seen in products until 1H 2026 assuming TSMC doesn't experience a single delay transitioning to GAA & BPD.

We'll just have to wait and see. Intel has an investor foundry call next week, we should know more then.

 

[Doug S]

We'll just have to wait and see. Intel has an investor foundry call next week, we should know more then.

We'll know more about what Intel CLAIMS, not when they will actually be mass producing chips that are superior to what TSMC is mass producing at that time. If you listen to that call and believe everything they say, you were probably pretty confused by how many years it took Intel to ship 10nm CPUs after claiming the process was ready and mass production a couple quarters away.

 

[moinmoin]

Intel isn't really in the open market competition for foundry customers yet. Things will get very interesting once IFS competes head on against TSMC for customers for leading edge processes.

 

[H433x0n]

We'll know more about what Intel CLAIMS, not when they will actually be mass producing chips that are superior to what TSMC is mass producing at that time. If you listen to that call and believe everything they say, you were probably pretty confused by how many years it took Intel to ship 10nm CPUs after claiming the process was ready and mass production a couple quarters away.

MTL will be out by October. Sierra Forest is currently sampling to customers. The Intel 3 / 4 node is waiting on products, not the products waiting for a node.

Intel 18A is still far enough out that there is room for things to go wrong but all of the metrics that you’re supposed to hit as far as defect rate at 12 months out from HVM have been hit.

 

[Doug S]

MTL will be out by October. Sierra Forest is currently sampling to customers. The Intel 3 / 4 node is waiting on products, not the products waiting for a node.

Intel 18A is still far enough out that there is room for things to go wrong but all of the metrics that you’re supposed to hit as far as defect rate at 12 months out from HVM have been hit.

Yes but the 3/4 node is what they were calling "7nm" back in the day - what roadmaps a decade ago showed arriving basically five years ago! So things have already gone very very wrong, and finally shipping Intel 3/4 in volume later this year won't change that. If they can hit schedule with 20A and 18A then I'll believe they've turned things around.