Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

www.anandtech.com

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

Samsung’s Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track

www.anandtech.com

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

 

[moinmoin]

It's possible that the base is an Intel node, I just think it's far more probable to be based on UMC's 14 nm node than Intel's. UMC's node will already have proven out 3rd party tools, quality external customer documentation, and support staff. As far as I know, this doesn't exist for Intel's 14 nm node. I think it makes far more sense for UMC to share their 14 nm recipe with Intel (this isn't something valuable to Intel) and tweak it a little with them which will require only minor updates to their flow, than it is for Intel to develop all of the design flow for 3rd party customers just for UMC to get a piece of the pie. This allows Intel to get use out of their aging foundries with minimal effort and UMC gets additional capacity, win-win.

It's Intel manufacturing in its existing foundries. I don't know how similar UMC's setup is to Intel's, but I would think aside big blocks like ASML machines they are actually very proprietary and not easily exchangeable. So I'd think it's Intel's node (14nm specifically) at the very least as a base. Then the question is whether it's faster and less costly to adapt Intel's node to UMC's tools or UMC's tools to Intel's node. While I expect both to happen to a degree, I'd think adapting UMC's tools would be faster and less costly, especially since UMC unlike Intel has a track record of supporting its customers with standardized tools and solutions. And that's also what IFS can and must learn from.

 

[Aapje]

My guess is that it's either Intel 10 with fewer repeat exposures or Intel 14 with more exposures. The 'x nm' naming is just made up anyway.

 

[igor_kavinski]

While I expect both to happen to a degree, I'd think adapting UMC's tools would be faster and less costly, especially since UMC unlike Intel has a track record of supporting its customers with standardized tools and solutions. And that's also what IFS can and must learn from.

Makes sense. Intel engineers need to learn how things are done in a standardized way to make their foundries more attractive to any external customer. Otherwise it just makes more sense for the customer to save time and go with TSMC.

 

[Hitman928]

It's Intel manufacturing in its existing foundries. I don't know how similar UMC's setup is to Intel's, but I would think aside big blocks like ASML machines they are actually very proprietary and not easily exchangeable. So I'd think it's Intel's node (14nm specifically) at the very least as a base. Then the question is whether it's faster and less costly to adapt Intel's node to UMC's tools or UMC's tools to Intel's node. While I expect both to happen to a degree, I'd think adapting UMC's tools would be faster and less costly, especially since UMC unlike Intel has a track record of supporting its customers with standardized tools and solutions. And that's also what IFS can and must learn from.

They all pretty much use the same machines. Intel doesn't make their own equipment for any of the manufacturing as far as I am aware (just like the other foundries). They may use different models or newer machines but they all have the same functionality. The difference isn't in the equipment (for similar nodes), it's in the exact recipe the researchers came up with and the foundries ability to keep things calibrated and tolerances tight. There have been multiple instances of one foundry using another foundry's process through a licensing agreement (e.g., GF 14 nm FinFET was actually Samsung's process which they licensed). Intel actually has an agreement with IBM now for access to IBM's process research on advanced nodes so Intel's nodes going forward should have at least some of IBM's fingerprints on them.

If Intel uses UMC's node, they need to obviously get the recipe from UMC and then run some verification wafers to make sure they get the process right and the developed tools give valid results. Pretty much all of the work is done and they just need to go through some minor tweaks and verification. If they base it off of Intel's nodes, they have to build out the entire 3rd party tool chain and support based on Intel's internal tools and then run through the same verification wafers. I think the shortest path is clearly through using UMC's node as the base. For that reason, as well as knowing that Intel is extremely guarded about sharing any details of their own processes with others, leads me to believe it is based on UMC's 14 nm node but I don't know for sure.

Makes sense. Intel engineers need to learn how things are done in a standardized way to make their foundries more attractive to any external customer. Otherwise it just makes more sense for the customer to save time and go with TSMC.

The foundry engineers and tools/support guys are completely separate teams. Intel won't learn how to be a 3rd party foundry if all of the design tool and customer facing work is handled by someone else.

 

[moinmoin]

The foundry engineers and tools/support guys are completely separate teams. Intel won't learn how to be a 3rd party foundry if all of the design tool and customer facing work is handled by someone else.

Sure, Intel won't learn if it just takes UMC's node and let UMC handle everything else.

 

[Hitman928]

Sure, Intel won't learn if it just takes UMC's node and let UMC handle everything else.

The node won’t even be available until 2027. This isn’t about Intel learning to be a 3rd party foundry, it’s about them filling old fabs to bring in additional revenue through fabs that would otherwise be deprecated. The easiest way to do that would be to let UMC handle everything up front and Intel fulfills the back end manufacturing. If Intel only feels comfortable running their own process through their fabs, then maybe that’s the path they take but then there’s significantly more work to be done to develop a customer PDK, IP catalog, etc.

 

[H433x0n]

https://twitter.com/x/status/1752490651768537328

The start of an IFS + Nvidia relationship.

 

[Doug S]

https://twitter.com/x/status/1752490651768537328

The start of an IFS + Nvidia relationship.

I think Nvidia would only reluctantly work with Intel, given that Intel is wanting to compete with them in AI. Since TSMC is not capacity constrained on N5 or N7 family nodes Nvidia is getting all the chips they want. They have little reason to go to Intel's foundry for wafers unless Intel can make them on a clearly better or clearly cheaper process, and guarantee they get as many as they want.

 

[Aapje]

Since TSMC is not capacity constrained on N5 or N7 family nodes Nvidia is getting all the chips they want. They have little reason to go to Intel's foundry for wafers unless Intel can make them on a clearly better or clearly cheaper process, and guarantee they get as many as they want.

The issue is not the actual wafer, but packaging the chiplets together to make the chip.

TSMC uses an expensive and very good process for this called CoWoS, but they have insufficient capacity.

Note that CoWoS is only used for these expensive chips and not for 'cheap' gaming chips like in the 7900 XTX.

 

[igor_kavinski]

ASML fires back at accusations that its next-gen High-NA EUV chipmaking tools are too expensive

Says their insertion into production flows is inevitable anyway.

www.tomshardware.com

Funny when ASML says, "Talk to Intel if you wanna know the real costs of double patterning!"

 

[jpiniero]

The issue is not the actual wafer, but packaging the chiplets together to make the chip.

Feels like a dubious rumor, mainly because I'm not sure you can just plug and play CoWoS with Foveros.

 

[Khato]

Agreed, switching from CoWoS to Foveros would almost certainly require some amount of redesign. But that redesign would likely only encompass one or two of the top metal layers no? And potentially a switch to Intel wafers for the passive carrier. NVIDIA had clear indicators of being capacity constrained by Q2 last year, so time frame is about right. It's quite feasible they'd invest a small-ish amount to see if Foveros is a viable alternative.

 

[FlameTail]

Otherwise it just makes more sense for the customer to save time and go with TSMC.

....or Samsung?

 

[Doug S]

The issue is not the actual wafer, but packaging the chiplets together to make the chip.

TSMC uses an expensive and very good process for this called CoWoS, but they have insufficient capacity.

Note that CoWoS is only used for these expensive chips and not for 'cheap' gaming chips like in the 7900 XTX.

I know that, I guess I wasn't clear. I was responding to the post claiming this was the start of an Nvidia + IFS relationship, implying it would go further into wafer supply. I think this is just a temporary relationship with Nvidia taking advantage of Intel's available packaging capacity, until TSMC has their additional capacity ready.

I wouldn't be surprised to see some of TSMC's overseas fabs have additional packaging capacity added to them - more than the fab they serve would need. That would allow e.g. Apple to ship leading wafers from Taiwan that TSMC isn't producing in the US to Arizona. Having them packaged in the US would increase the "made in America" content at little additional expense to Apple since packaging is almost entirely automated.

 

[Aapje]

Feels like a dubious rumor, mainly because I'm not sure you can just plug and play CoWoS with Foveros.

I'd agree if this was about consumers graphics cards rather than AI cards with insane demand and margins.

Doing a bit of a redesign and a lot of extra validation seems like a small price to pay for the potential upside of selling a ton more at highly inflated prices.

 

[FlameTail]

ASML fires back at accusations that its next-gen High-NA EUV chipmaking tools are too expensive

Says their insertion into production flows is inevitable anyway.

www.tomshardware.com

ASML hits back at Semianalysis.

High NA EUV better than Low NA EUV double patterning.

 

[Doug S]

ASML fires back at accusations that its next-gen High-NA EUV chipmaking tools are too expensive

Says their insertion into production flows is inevitable anyway.

www.tomshardware.com

ASML hits back at Semianalysis.

High NA EUV better than Low NA EUV double patterning.

I guess they are worried Semianalysis' take would hurt their stock price.

That's the only reason they would care to provide their rebuttal to that article, because they aren't going to convince their customers. TSMC, Intel, et al will figure out which is the more cost effective path for them, they don't care what Semianalysis or ASML think.

 

[Aapje]

That's the only reason they would care to provide their rebuttal to that article, because they aren't going to convince their customers. TSMC, Intel, et al will figure out which is the more cost effective path for them, they don't care what Semianalysis or ASML think.

ASML don't build new machines without serious commitments from their customers anyway.

It's not like TSMC, Intel, Samsung and such read reviews after the machines have already been developed, like we read/watch GPU/CPU reviews. They know exactly what is being developed and have made their own analysis of the upsides and downsides of the new machines.

 

[FlameTail]

Also that Semianalysis article came out weeks (or months?) ago, so any possible damage to the stock price has already been done.

 

[Hitman928]

Intel delaying their new fab in Ohio by at least two years. Intel statement: ""Our decisions are based on business conditions, market dynamics and being responsible stewards of capital." Analyst believes it is due to a lack of demand for Intel fab space.

Intel delays $20B chip facility in Ohio - WSJ

Intel (INTC) has delayed the construction of its $20 billion chip-manufacturing project in Ohio, impacting the companys timeline.

seekingalpha.com

Intel's Ohio delay likely due to excess capacity, not roadmap concerns: analyst

Intel delays construction of $20B chip facility in Ohio due to slower chip market, signaling a reset in revenue expectations.

seekingalpha.com

 

[Tigerick]

Intel delaying their new fab in Ohio by at least two years. Intel statement: ""Our decisions are based on business conditions, market dynamics and being responsible stewards of capital." Analyst believes it is due to a lack of demand for Intel fab space.

Intel delays $20B chip facility in Ohio - WSJ

Intel (INTC) has delayed the construction of its $20 billion chip-manufacturing project in Ohio, impacting the companys timeline.

seekingalpha.com

Intel's Ohio delay likely due to excess capacity, not roadmap concerns: analyst

Intel delays construction of $20B chip facility in Ohio due to slower chip market, signaling a reset in revenue expectations.

seekingalpha.com

And why is IFS having excess capacity? At the meantime, TMSC is having EUV machines constraint for N3E process cause as I listed here, TSMC has received almost all business from OEMs including Intel. Intel so far has been pretty much confirmed to order 3 EUV machines in order to produce LNL, ARL 8P+16E and ARL 8P+32E.

Meanwhile, IFS is having more than 10 EUV sitting idle without orders....At first I thought MTL would start Intel's EUV aggressive roadmap, but all signs are indicating IFS is not capable of producing competitive SoC. Sorry if there is Intel's shareholders in this forum, better run ASAP...

 

[FlameTail]

Intel delaying their new fab in Ohio by at least two years. Intel statement: ""Our decisions are based on business conditions, market dynamics and being responsible stewards of capital." Analyst believes it is due to a lack of demand for Intel fab space.

What we're we expecting?

It's OHIO

 

[coercitiv]

Intel delaying their new fab in Ohio by at least two years. Intel statement: ""Our decisions are based on business conditions, market dynamics and being responsible stewards of capital." Analyst believes it is due to a lack of demand for Intel fab space.

It's important to remember that just 2 years ago Intel was aiming to slowly reduce US and EU reliance on Asian foundries over the next decade, to a point where US and EU combined would provide 50% of the global supply, up from just 20%:


Back then it was all about lobbying for state funds to build new foundries, now they're discovering market dynamics and responsible capital spending.

 

[Aapje]

Back then it was all about lobbying for state funds to build new foundries, now they're discovering market dynamics and responsible capital spending.

Things are different when it's your own money.

I have the same issue with current GPU prices.

 

[Dayman1225]

The slow rollout of the CHIP acts funding is likely playing a large roll in this delay as well. Funds were expected to be allocated before the end of last year IIRC