Aside from what IDC has already intimated, it's probably also useful to know that "double patterning" is a general term for an industry-understood technique, but it doesn't actually refer to just one and only one "thing", which further complicates answering the question "what's the min pitch for double patterning?". We could be talking about cut masks, spacer double patterning, or the double 'litho-etch' process that you probably have in mind (i.e, litho-etch-litho-etch double patterning).
Intel's been using cut masks for their double patterning, and this requires one mask to pattern a one-dimensional grating, + another mask (or more, depends on desired pitch) to cut the grating for the layout. Intel's been doing this since 45nm. I can't be sure about this, but this is probably why they were able to avoid immersion litho at 45nm. I'm not really the authority to determine that, though, so all I can say is I'm pretty sure, for whatever that's worth (not much ).
Spacer I've also heard it called 'self-aligned' double-patterning is a different beast, although perhaps it's best described as an "add-on" to the cut mask litho. The gratings from before have spacers deposited on them, the effect of which is that pitch reduction isn't due to the additional litho step. Intel's uses this for their fins.
Naturally, since the spacer dp is the upgrade to the cut masks one, the spacer dp has a much lower min pitch limit, in a reasonable sense ('reasonable' being something actually usable, resulting in a non-ridiculous set of transistors/IC's). The cut masks with only traditional litho was good for about 80nm pitch (using 1D gratings, 2D patters will of course be worse off, probably 50-60% bigger, I'm not sure). Using spacer dp, it's feasible to go smaller. Hmmm... actually, I'm not sure right now. I had something off the top of my head but can't remember it straight. I'm pretty sure it's continued use in smaller and smaller nodes is all but guaranteed, since adapting the process for smaller and smaller pitches just requires more etch and spacer deposition. Of course, I say just requires as if it's simple, but it's the result of amazing engineering talent and lots of money; what I really mean is that the process made is brilliant that it is extendable to lower nodes more easily than competing processes.
In the non-Intel world, as far as I know only memory (the simple beasts that they are) uses some sort of spacer double-patterning. (I could be wrong, so again, random internet dude, take it for what it's worth.) So in non-memory IC's, the non-Intel fabs has what I just end up calling "straight-up" double patterning, because they literally do litho-etch-litho-etch. It's honestly sort of a let-down once you've already gone through the Intel stuff, because compared to it, it's not as "hey that reads amazing!" as the Intel ones. Here, for example, your physical layout has to be designed with awareness that it (the layout) will be split into two masks, that's a pain. It's also far less extendable than spacer double-patterning, requiring additional litho and etch steps for every additional pitch reduction, and litho and etch equipments are priced off the roof, so you can't just add more and more just because you want/need to, you'll quickly run into a brick wall called economics.
Anyway, this is the roundabout way of answering your question that Idontcare already succinctly answered. It's impossible to answer your question literally because there's no "one-true double-patterning process", and it depends on design rules and what trade-offs the particular foundry chose to make or have made in the past that carried over to their new nodes, and how much money is considered "reasonable", and how much pain (for the foundry and customers) is acceptable (such as porting IP for new design rules to facilitate lower metal pitches). Foundries can repeat litho-etch until the cows come home (assuming they want to spend that kind of money) and produce a minimum metal pitch that rivals what Intel can produce or even smaller, but that's not to say it's not going to bankrupt them or make their $/transistors metric shoot up and make all their customers switch to another foundry.