LLC confusion and problems

[bononos]

This times a million. Just leave it alone. Increase only the vcore offset and that's it.

Why do mb's have the llc option then?

 

[Idontcare]

Why do mb's have the llc option then?

Leaving it alone is also not the right answer because in some cases the motherboard will default to the most aggressive level of LLC and the overshoots are ridiculous on the high-side. (as was the case with my MIVE-Z)

One may not like the notion or concept of LLC, but one cannot simply ignore it either. Not without elevating the risk to their CPU.

Yeah, figure 3 is pretty amazing. That you have these detectors all over the place and you can get massively different readings depending on where you are... I mean, it makes intuitive sense, but seeing it - and seeing the magnitude of the delta - is something else. Previously I had this idea that a grid is a grid and pretty much all the points to pull power from move more or less together and droop was createdout on the external regulator. I don't think that I'd really internalized how much of a delta you could get on chip in a specific region (unless you messed up the grid by forgetting to contact it or something) but then you see how much of a delta there is across the die and you can see how large a delta you can get within a die over a short period of time.

I meant to comment on the magnitude of the delta as well. It was easily a whole order of magnitude higher than the absolute worst-case I had assumed it would be.

I was expecting something on the order of hundreds of microvolts of droop, not something on the order of tens of millivolts

No wonder Intel specs the Vcc to be so large, seemingly, when they bin their chips in comparison to how much undervolting we enthusiasts find ourselves comfortable with when we run a rather unqualified "stress test" and declare our 0.8V 4GHz 3770K to be "stable" :whiste:

There is a solid 0.1V of margin Intel needs to build into their Vcc spec just to ensure they've got the intra-die Vdroop covered. Simply fascinating.

I also couldn't help but wonder just how much of this "droop net" technology has made its way into Haswell, complete with the necessary analog logic being added to the existing power regulation circuitry in the established PCU, to couple synergistically with the on-package VRMs to minimize power-consumption by reducing the necessity of maintaining such a large Vcc margin as needed to counter-act the intra-die droop... I see opportunity to do very elegant and sophisticated stuff there.

 

[taq8ojh]

Leaving it alone is also not the right answer because in some cases the motherboard will default to the most aggressive level of LLC and the overshoots are ridiculous on the high-side. (as was the case with my MIVE-Z)

I am still not quite sure how to approach this. Higher LLC setting means higher vcore, so I'd have to use negative offset. Lowest LLC setting means I have to use positive offset. Logic says the result will be identical, however in theory based on what I read, high LLC is a must. Eh.

 

[2is]

LLC is only applied at load vs offset which is "always on"

Negative offset + LLC can often time lead to instability at low load situations since LLC isn't active and your negative offset has dropped your voltage to less than what's necessary for stability.

Positive offset with no LLC is usually fine (and preferred IMO) for mild overclockes. At higher clock speeds using +offset only, you end up running running way more than necessary voltage at low/no load in order to compensate for vdroop during high load.

At 4.2GHz I ran a +.025 offset with no LLC. At 4.3 I ran a +.020 with LLC at its lowest setting. This combination gives me stable voltage at low/no load without over-voting and enough voltage at load so that vdroop isn't causing problems.

 

[taq8ojh]

Hmm. Interesting. Guess I gotta try both.
I am currently trying for 4.4GHz, which is questionable amount of overclock, so it would be nice to hear various opinions on that.

 

[tracerbullet]

I have a linked saved from some time ago ( http://hardforum.com/showpost.php?p=1036997079&postcount=329 ) and always thought this part of it was interesting (post 329, user "silkysean"):

I've been doing some research.... I know that I can run 4.8Ghz stable at 1.368v under load, so
LLC on REGULAR and Offset @ +0.140 = 1.368v under load (1.088 on idle) PRIME STABLE
LLC on MEDIUM and Offset @ +0.095 = 1.368v under load (1.040 on idle) PRIME STABLE
LLC on HIGH and Offset @ + 0.060 = 1.368v under load (1.000 on idle) PRIME STABLE
LLC on ULTRA HIGH and Offset @ + 0.025 = 1.368v under load (0.982 on idle) - BSOD
LLC on EXTREME and Offset @ - 0.020 = 1.368v under load (INSTANT DEATH)

I vaguely remember a few others here on AT describing better results with LLC off / all the way down as well.

 

[taq8ojh]

Your overclock is pretty extreme though

There are SO many variants to experiment with I don't know where to start. All I know is I never had idle crashes of any kind with any settings I tried so far - so higher LLC is probably still not out of question yet.

So far the best results for 4.4GHz were:
LLC on lowest with 0,040V offset, resulting in Prime95 error after 21,5 hours
and
LLC on 2nd highest with -0,045V offset, resulting in Prime95 error after 17 hours
Interesting fact is stability is obviously not increasing with vcore, in fact it's completely random: -0,040V offset crapped out on me after just two hours, but -0,035V lasted 11 hours.
Guess I will have to test every single offset in some decided range, because stability might lie anywhere.

 

[CTho9305]

Motherboard-level transients are probably going to be on the order of less than one microsecond to a few microseconds. Definitely not milliseconds.

Even this doesn't get you an accurate measurement
because it will give you only the coarse measurement that you can get off chip. For true accuracy, you need to measure it on-die.

We used this technique on a prior design that I was involved with:
https://www2.lirmm.fr/lirmm/interne/BIBLI/CDROM/MIC/2009/ITC_2009/Papers/PDFs/0008_2.pdf

I spent a bit of time about two years ago getting the ODDD and ODDI systems described in the paper work on a more recent microprocessor and the whole thing is really cool.

I think I saw that paper (or another one on the same technology) when I was at my last job, and it lead to some interesting lunch discussions!

 

[Mark R]

Hmm, wonder if that is why mobo makers are still putting huge VRMs on Haswell motherboards - trying to reduce overshoot (or at least have an even better critically damped signal). If so, this could really help with Haswell overclocking. I would assume that the on-board VRM would be faster than the mobo based VRMs. Can't wait for review.

Haswell still needs a low voltage (2.4V) to be delivered to the socket, so a large step-down voltage converter is required to convert the 12V delivered to the motherboard into 2.4V for the Haswell socket.

Adding more phases to a voltage converter is an easy way to improve maximum current capacity, while avoiding the use of expensive high-current components. You also get a side benefit of improving response speed and voltage ripple, as well as providing more flexibility in PCB design.

 

[Ajay]

Haswell still needs a low voltage (2.4V) to be delivered to the socket, so a large step-down voltage converter is required to convert the 12V delivered to the motherboard into 2.4V for the Haswell socket.

Adding more phases to a voltage converter is an easy way to improve maximum current capacity, while avoiding the use of expensive high-current components. You also get a side benefit of improving response speed and voltage ripple, as well as providing more flexibility in PCB design.

Thanks!

 

[2is]

LLC is only applied at load vs offset which is "always on"

Negative offset + LLC can often time lead to instability at low load situations since LLC isn't active and your negative offset has dropped your voltage to less than what's necessary for stability.

Positive offset with no LLC is usually fine (and preferred IMO) for mild overclockes. At higher clock speeds using +offset only, you end up running running way more than necessary voltage at low/no load in order to compensate for vdroop during high load.

At 4.2GHz I ran a +.025 offset with no LLC. At 4.3 I ran a +.020 with LLC at its lowest setting. This combination gives me stable voltage at low/no load without over-voting and enough voltage at load so that vdroop isn't causing problems.

Just wanted to updated this. My 4.3GHz clocks weren't as stable as I thought. The computer would often reboot when exiting out of a game. (so going from a load state to a sudden idle state) I initially thought it was something wrong with my new SLI setup, but decided to back it off to 4.2 +.025 no LLC before trying anything else since I had not done anywhere near as much stability testing at 4.3 as I did with 4.2, and sure enough, the problem went away.

I'm sure another step or two on the offset would have cured the issue as well, but not worth it for an extra 100MHz, especially since during our summer like heat wave the last couple days, I was already hitting mid 90's in IBT at my unstable voltages.