LOL look at this noob's overclock Q6600

[BadRobot]

Originally posted by: LOUISSSSS
okay so i'm at 3.6ghz right now with BIOS vcore at 1.375 and cpu-z reading of 1.328 (why is it so much lower than the bios reading?

Vdroop makes your volts drop some...for a better explanation...uh..google vdroop =)

 

[LOUISSSSS]

Originally posted by: Assimilator1
Don't count on it ,if you play any modern-insh games then a combination of CPU load & more importantly the extra heat given off by the graphics card could easily push your CPU temps that high.Only way to be certain is to test it out.

Btw 68C is within safe limits ,but not by much! , 71C is considered the maximium by many.
Personally I wouldn't go that high but then I load my CPU 24/7 ,365 days a year (well almost) for years on end.
I guess you need to weigh up whether the higher temps it runs at is worth the extra speed you gain ,how long you plan to keep it & how often it'll be heavily loaded.

Oh btw ,I'm jealous ,I want 3.6GHz too! (mine's at 3GHz).

Sickbeast
Very true ,were you overclocking in the days before the PCI bus could be locked? man what a nightmare that could be! can't believe I used to run a S7 TX mbrd at 83MHz with a 41.5MHz PCI bus!:Q.......& without problems!

my gpu won't heat up my cpu.. 8800gt is mounted above the cpu socket when mb is upside down

 

[Assimilator1]

It will heat up the case air though ,unless you have the side off or have lots of case cooling.
Btw vdroop is partly the result of the CPU taking so much power that the mbrd cant keep the voltages dead steady ,for a better explanation google it

 

[BadRobot]

Originally posted by: Assimilator1
It will heat up the case air though ,unless you have the side off or have lots of case cooling.
Btw vdroop is partly the result of the CPU taking so much power that the mbrd cant keep the voltages dead steady ,for a better explanation google it

Some people try to suggest that vdroop is a "working as intended" side effect put in place by intel...

 

[Assimilator1]

lol ,you're kidding me!? ,side effect of CPU load more like,& intended not!

 

[10acjed]

Great topic.
Ive been debating getting a Q6600, and putting it on my S3 board.

Hopefully will be able to next week. Ill let you know how it goes.

 

[soccerballtux]

bumping old thread = lose lol.

N00b poster at anandtech = win. Welcome!

 

[Idontcare]

Originally posted by: Assimilator1
lol ,you're kidding me!? ,side effect of CPU load more like,& intended not!

http://download.intel.com/desi.../datashts/31559205.pdf

Actually its pretty clear why Vdroop exists and it is well documented and specified in Intel's published Q6600 processor datasheets. I refer you to section of the link, look in the neighborhood at pages 20 and 21.

Even your household electrical lines experience Vdroop. If you place a load on an outlet, say plug-in a hairdryer, and measure the Voltage on the same circuit at another outlet you will see that the Voltage drops some 2-5V.

This phenomenon is called a "brown-out" and when it gets too severe then the voltage gets too low for devices to operate and that is when it becomes a national headline that a brownout has occured.

Don't blame the CPU or the mobo makers for not violating the laws of physics. Trust me they'd love to figure out how to do that for you.

 

[Martimus]

Originally posted by: Idontcare

Originally posted by: Assimilator1
lol ,you're kidding me!? ,side effect of CPU load more like,& intended not!

http://download.intel.com/desi.../datashts/31559205.pdf

Actually its pretty clear why Vdroop exists and it is well documented and specified in Intel's published Q6600 processor datasheets. I refer you to section of the link, look in the neighborhood at pages 20 and 21.

Even your household electrical lines experience Vdroop. If you place a load on an outlet, say plug-in a hairdryer, and measure the Voltage on the same circuit at another outlet you will see that the Voltage drops some 2-5V.

This phenomenon is called a "brown-out" and when it gets too severe then the voltage gets too low for devices to operate and that is when it becomes a national headline that a brownout has occured.

Don't blame the CPU or the mobo makers for not violating the laws of physics. Trust me they'd love to figure out how to do that for you.

There are definitely ways to avoid that with the design, but it can get expensive and a little complicated. I would draw you up a circuit design with some simple op-amps to keep a rock solid Vout, but I can't exactly do that here. For my second internship years ago, my boss had me do that before he gave me the job. I worked on designing power regulator circuits for an airbag module at that time. (That job was actually pretty fun, unlike my current job )

 

[Idontcare]

At *best* you are talking about reducing the time regime for which the Vdroop would occur while your attempted to counter-act the load. You are not talking about eliminating it, merely minimizing its transient existance.

And if you do it such that the transients lifetime is less than the sampling rate of your o-scope (or your software on your computer) then you'd merely be blind to its occurance. Blissfully ignorant I suppose, but nonetheless the Vdroop transient will still exist.

Would you agree? Or are your circuits time travelers that go back in time and tell itself when to predict the CPU is about to become loaded with sub atto-second time resolution?

My Asus P5E WS Pro has loadline calibration which does exactly what you are suggestion, it monitors the loads and ups the voltage to compensate. But you want to guess what the voltage transient to the high-side looks like when the load on the CPU ends? It's not pretty and it is exactly what Intel is intentionally trying to avoid by ensuring mobo makers allow Vdroop to occur.

 

[Assimilator1]

As mentioned this is an old thread, I've since read the article Anandtech wrote about vdroop, & the explanation for allowing it to happen made sense to a degree.

Funny how we've only really noticed it with more modern (more power hungry) CPUs.....

 

[Idontcare]

Hey there was a time when nobody on this planet knew what load induced voltage drops meant...every single person who knows something about know spent a considerable portion of their lives not knowing jackshizzy about it, including me.

I don't think anyone is expecting folks to explain their posting past, we are all changing people.

I bet I got some real ridiculous posts in my history bin here at the forums if someone wanted to sift thru them

 

[Martimus]

Originally posted by: Idontcare
At *best* you are talking about reducing the time regime for which the Vdroop would occur while your attempted to counter-act the load. You are not talking about eliminating it, merely minimizing its transient existance.

And if you do it such that the transients lifetime is less than the sampling rate of your o-scope (or your software on your computer) then you'd merely be blind to its occurance. Blissfully ignorant I suppose, but nonetheless the Vdroop transient will still exist.

Would you agree? Or are your circuits time travelers that go back in time and tell itself when to predict the CPU is about to become loaded with sub atto-second time resolution?

My Asus P5E WS Pro has loadline calibration which does exactly what you are suggestion, it monitors the loads and ups the voltage to compensate. But you want to guess what the voltage transient to the high-side looks like when the load on the CPU ends? It's not pretty and it is exactly what Intel is intentionally trying to avoid by ensuring mobo makers allow Vdroop to occur.

I have actually responded to this twice, but decided to avoid posting it because both of them made it sound like you really don't know what you are talking about, and I don't want to make anyone look bad. At the same time, what you said was somewhat condescending, and annoyed me enough that I am writing back after seeing it again. You obviously undestand loading issues, but there are ways around that without using magical time travel. You can get a very well regulated output on an opamp without regards to the load as long as the load is within the operational limits of the opamp. With enough power available, and good enough filters in place you should be able to avoid any noticable drops under load. That being said, designing a circuit for that precise of a voltage (especially at such low voltages) with such huge power demands would be very complex, thus being very expensive to manufacture. For my line of work, that would make sense; for MB's it wouldn't.

edit: I didn't mean to sound harsh, what I was trying to say was that you don't need an intellegent active voltage regulation to keep a clean signal (which is what you seem to be saying the ASUS board has). You really just need enough power to run it at its maximum, and good enough filters to keep the Output from dropping beyond spec when it is loaded.

 

[Idontcare]

Martimus sorry to have caused you such consternation. There's no point having a discussion if folks feel they are being slighted against, my comments were intended to be read as tongue in cheek.

 

[Martimus]

Originally posted by: Idontcare
Martimus sorry to have caused you such consternation. There's no point having a discussion if folks feel they are being slighted against, my comments were intended to be read as tongue in cheek.

It is ok, I apologize that I took offense.

 

[Idontcare]

Originally posted by: Martimus
edit: I didn't mean to sound harsh, what I was trying to say was that you don't need an intellegent active voltage regulation to keep a clean signal (which is what you seem to be saying the ASUS board has). You really just need enough power to run it at its maximum, and good enough filters to keep the Output from dropping beyond spec when it is loaded.

Does that solve the issue of Vcc overshoot? When the circuit unloads how do you prevent the CPU (which becomes a massive capacitor in nanoseconds) from inducing large voltage spike to the upside on those fragile gate oxides?

This is the part I don't get, how you can have your cake and eat it too. And if it is possible, why would Intel act like they never heard of it before? Surely a dual-socket server board is high enough margin to warrant figuring out how to run Vnom closer to Vmin by minimizing Vdroop while not jeopardizing the CPU over Vcc overshoot.

Why would Intel not pursue? Is it space issue for the components you are envisioning using to do this?

 

[Markfw]

Idontcare, I see where Intel documents how the expected vdroop may happen, how long and how much voltage can vary. But the fact is, you CAN have a motherboard that has NO vdroop, and I own 3 of them (DQ6, there are other models I am sure). As I see it, its just more expensive to have a great power source where this doesn't occur.

 

[Martimus]

Originally posted by: Idontcare

Originally posted by: Martimus
edit: I didn't mean to sound harsh, what I was trying to say was that you don't need an intellegent active voltage regulation to keep a clean signal (which is what you seem to be saying the ASUS board has). You really just need enough power to run it at its maximum, and good enough filters to keep the Output from dropping beyond spec when it is loaded.

Does that solve the issue of Vcc overshoot? When the circuit unloads how do you prevent the CPU (which becomes a massive capacitor in nanoseconds) from inducing large voltage spike to the upside on those fragile gate oxides?

This is the part I don't get, how you can have your cake and eat it too. And if it is possible, why would Intel act like they never heard of it before? Surely a dual-socket server board is high enough margin to warrant figuring out how to run Vnom closer to Vmin by minimizing Vdroop while not jeopardizing the CPU over Vcc overshoot.

Why would Intel not pursue? Is it space issue for the components you are envisioning using to do this?

Yes. It will work both ways, if you account for that issue in your design. The reluctance of your filters will keep it from spiking or dropping quickly, especially if higher quality components are used. But the real issue is that the Opamp can't supply more voltage than it is supplied, and your voltage input is seperated from the power input to keep issues like this from affecting the loading voltage. At least that is how I designed important power supplies that were known to draw enough power to load the line. You just seperate the power and input signals, so that loading one won't load the other. I know that I didn't come up with this concept, as it was another engineer at the company I worked at that showed me how to do it, so it is probably pretty common.

 

[Idontcare]

Originally posted by: Markfw900
Idontcare, I see where Intel documents how the expected vdroop may happen, how long and how much voltage can vary. But the fact is, you CAN have a motherboard that has NO vdroop, and I own 3 of them (DQ6, there are other models I am sure). As I see it, its just more expensive to have a great power source where this doesn't occur.

We are not in disagreement...I'm not saying Vdroop isn't avoidable...in fact I mentioned in my post that my P5E WS Pro has loadline calibration and avoids Vdroop as well. It's a big help in overclocking my voltage hungry B3 Kentsfield.

 

[LOUISSSSS]

i'm back into OC'ing after a fresh format and a bios update to latest DS3P Bios (F10)

i've pretty much stopped using p95 v25.6 and switched to OCCT v2.0.0b.b01 (its a beta)
from experience, any errors caught in OCCT within 2 hours of testing will eventually be caught by p95 in 6-12 hours. Hence, i've been sticking to OCCT Ram/CPU testing.

my current stable settings for my Q6600 G0 (1.2125 VID) are:
CPU clock: 400FSB x 8 = 3.2ghz
RAM clock: 400mhz 1:1 4-4-4-12
Bios: 1.300v
CPU-Z: idle: 1.248v
CPU-Z load: 1.232v
Ram: 2.2v
Loadline Calibration: Disabled

Temps:
Room: 68-70F
Real Temp v2.24 Load: 60c,51c,51c,60c