How do I replace teh lazors.they need to speed up the integration of optical
mehh, prices go down quickly.According to this, 32 GB of LPDDR6 LPCAMM3 will cost $500 apiece.
[News] New Standard for DDR6 Memory to Come out Soon | TrendForce Insights
JEDEC (the Solid State Technology Association) recently confirmed that the long-used SO-DIMM and DIMM memory standards will be replaced by CAMM2 for D...www.trendforce.com
According to this, 32 GB of LPDDR6 LPCAMM3 will cost $500 apiece.
RIP.
RIP DDR5 as well, did you see the prices they were charging for that when it first appeared!
Wait, what...DDR5 is everywhere? How is that possible when it was declared RIP based on launch pricing??
LPDDR5X -> LPDDR6
16 bit channel -> 24 bit channel
I speculate that the channel width will increase again, either in the LPDDR6X or LPDDR7 generation (likely the latter).
LPDDR6->LPDDR7
24 bit channel -> 32 bit channel
Chefe, pins ain't free.LPDDR6->LPDDR7
24 bit channel -> 32 bit channel
If you think that you have zero understanding of why the channel width was increased.
Yep. Narrower channels -> better bandwidth utilizationSince @FlameTail laugh reacted to this I'll spell it out for him.
Channel width is irrelevant in isolation. If you want x bandwidth you'll provide the necessary width via multiple controllers, so there is no benefit to the controller being wider. Indeed, there is benefit to it being narrower, which is why you saw DDR4 with a 64 bit wide channel -> DDR5 with 2x 32 bit wide channels -> DDR6 rumored to have 4 channels (which I'm betting will be 24 bits wide because 16 bit wide channels create certain implementation difficulties for ECC) That allows more independent memory accesses at a given overall width, which you want when you have a lot of cores that are working on different things.
The reason LPDDR6 went to 24 bit channels was simple math. They decided they wanted the flexibility of having additional bits to implement ECC or whatever else the host might want such as memory tagging. Theoretically they could have stayed with 16 bit channels and increased burst length to BL17/BL34, but that creates its own set of problems. Those problems were avoided with 24 bit wide channels and BL24. That math works out much better and creates the same 16 bits per 256 for host usage.
Had they not wanted those host bits they would have stayed with 16 bits, because there is no difference in building e.g. an Apple M4 with 128 bit wide memory that consists of 8 16 bit controllers or of 4 32 bit controllers. There would be almost no difference in die space or power. But there would be a cost in how many independent loads/stores could be in progress at once, with only half as many possible on the system with 32 bit controllers.
Core interconnects will likely be moving to a wireless standard within the decade and are quite a bit more sensitive to timing. The same technology should be easily transferrable to RAM usage. Wireless interconnects are being demonstrated to connect up to 25mm point to point. By using timing of individual points and modulation of the signal array its possible to pack these tranmitters and receivers in tight, dense arrays. We are talking pretty insane switching speeds compared to those seen relative to memory rates, so this will not be an exotic solution. Its about creating a future proof standard that abstracts physical memory types. I simply believe the solution being pushed for interconnects should be redirected at the memory bus. The industry would be turned on its head imho, once memory abstraction occurs. But to me its a natural focus of effort towards the path of least resistance.Cheap optical transceivers have unacceptable latency for main memory use. The universal standard connector for the next memory generation will be CAMM. Maybe there will be cheap low-latency transceivers for the DDR7 generation, but I doubt that.