Makefile issues

[toughwimp11]

This isn't really an urgent issue but I'm trying to learn to make better Makefiles and I've run into an issue and I have no idea why it's happening. I have the following makefile:

CC = gcc
CFLAGS = -Wall -g -std=gnu99 -lpthread

.PHONY: all clean

all: tests

tests: timerQueue.o test1.c test2.c
    $(CC) $(CFLAGS) -o test1 test1.c timerQueue.o
    $(CC) $(CFLAGS) -o test2 test2.c timerQueue.o

test1: tests
    echo "Running test 1...\nEnd with ctrl-c"
    ./test1

timerQueue.o: timerQueue.c timerQueue.h
    $(CC) $(CFLAGS) -c -o timerQueue.o timerQueue.c

clean: 
    @rm -f *.o test1 test2 *~

Now the 'problem' is that every time I run make, it remakes the tests even if nothing changed. I'm trying to understand why this is happening since the dependencies clearly don't change. any ideas?

 

[chronodekar]

Are you making any changes between the make runs or did you try running "make" twice in a row ?

-chronodekar

 

[degibson]

all: tests

tests: timerQueue.o test1.c test2.c
    $(CC) $(CFLAGS) -o test1 test1.c timerQueue.o
    $(CC) $(CFLAGS) -o test2 test2.c timerQueue.o

test1: tests
    echo "Running test 1...\nEnd with ctrl-c"
    ./test1

Target 'tests' never exists, so Makefile tries to make it every time you run make. Thats why it rebuilds the tests every time.

Try this instead:

all: test1 test2

test1: timerQueue.o test1.o
    $(CC) $(CCFLAGS) -o $@ timerQueue.o test1.o

test2: timerQueue.o test2.o
    $(CC) $(CCFLAGS) -o $@ timerQueue.o test2.o

test1.o: test1.c
    $(CC) $(CFLAGS) -c $< -o $@  

test2.o: test2.c
    $(CC) $(CFLAGS) -c $< -o $@

run_test1: test1
    @echo "Running test 1...\nEnd with ctrl-c"
    ./test1

Caveat: Our beautiful new code window doesn't include tabs... so I used spaces. Make won't like that if you copy and paste.

 

[dinkumthinkum]

Also mark non-existent targets with a declaration:

.PHONY all
all: ...