Discussion Mediatek SoC thread

[GTracing]

Is this the MediaTek thread? or the Apple thread?

 

[Nothingness]

Is this the MediaTek thread? or the Apple thread?

It can be argued that we discuss MediaTek competition, though I agree I might have gone a bit too far

 

[FlameTail]

Nvidia and MediaTek collaborate on 3nm AI PC CPU — chip reportedly ready for tape-out this month

Years of rumors may finally prove true.

www.tomshardware.com

According to reports from leakers on the Chinese social media site Weibo, Mediatek and Nvidia are collaborating on a 3nm AI CPU. IT Home shared a report from user "Mobile Chip Expert" today, claiming that the CPU is entering the tape-out phase of production this month, with mass production on track for late 2025.

If it's taping out this month, it's gotta be using the Cortex X925 core, not it's successor surely?

Mass production in late 2025 doesn't sound good either. That means it will come to laptops in early 2026. Basically launching alongside the 2nd generation Snapdragon X. I thought Mediatek/Nvidia might release it sometime in 2025 itself. It would have been strategic if they did so.

If that rumour is true, both Snapdragon X 2nd gen and Mediatek/Nvidia's SoC will be coming to notebooks in 2026. I don't think there'll be any significant growth in ARM notebook marketshare in 2025.

 

[mvprod123]

Nvidia and MediaTek collaborate on 3nm AI PC CPU — chip reportedly ready for tape-out this month

Years of rumors may finally prove true.

www.tomshardware.com

If it's taping out this month, it's gotta be using the Cortex X925 core, not it's successor surely?

Mass production in late 2025 doesn't sound good either. That means it will come to laptops in early 2026. Basically launching alongside the 2nd generation Snapdragon X. I thought Mediatek/Nvidia might release it sometime in 2025 itself. It would have been strategic if they did so.
View attachment 109240
If that rumour is true, both Snapdragon X 2nd gen and Mediatek/Nvidia's SoC will be coming to notebooks in 2026. I don't think there'll be any significant growth in ARM notebook marketshare in 2025.

There will be no growth until there is enough optimised software.

 

[DZero]

There will be no growth until there is enough optimised software.

Just is what is about to pull Huawei in their Harmony Os Next

 

[Doug S]

One could do that with 32-bit Arm.

Exactly. AArch64 cleaned up a few things in AArch32 but there was nothing stopping Apple from implementing highly aggressive SoCs without going 64 bit. What they couldn't do is have a viable plan to put them in Macs in the future since while they probably assumed phones could avoid going over 4 GB until the next (now current) decade, Macs were already there.

 

[FlameTail]

Rumour: Mediatek has supposedly stopped pursuing plans to make a flagship chip on Intel's nodes.

Not sure about that sentence before the last though...

 

[mvprod123]

Lol

https://twitter.com/x/status/1845491635901382980

 

[jdubs03]

Not too shabby.

https://twitter.com/x/status/1845811220831748135

 

[FlameTail]

MediaTek confident Dimensity 9400 can compete with Qualcomm

MediaTek has officially launched its Dimensity 9400 chipset, which it is confident can compete with Qualcomm's Snapdragon 8 Gen 4, launching later this month.

www.digitimes.com

~1 week to see if their confidence was placed right, or not.

The 9400 is equipped with one Arm Cortex-X925 core with a peak frequency of 3.62GHz, three Cortex-X4 cores reaching up to 3.3GHz, and four Cortex-A720 cores with a maximum frequency of 2.4GHz.

I still haven't come around to accepting the fact that is reusing last year's microarchitectures for 7 out of the 8 CPU cores in the Dimensity 9400. Puzzling.

 

[The Hardcard]

MediaTek confident Dimensity 9400 can compete with Qualcomm

MediaTek has officially launched its Dimensity 9400 chipset, which it is confident can compete with Qualcomm's Snapdragon 8 Gen 4, launching later this month.

www.digitimes.com

~1 week to see if their confidence was placed right, or not.


I still haven't come around to accepting the fact that is reusing last year's microarchitectures for 7 out of the 8 CPU cores in the Dimensity 9400. Puzzling.

The A720s were reworked and has a different performance curve. I forgot which one, but one poster claimed the Geekerwan video showed virtually the same performance as Apple’s e core for virtually the same power in SPEC. I didn’t notice that and have been planning to rewatch it.

That would be an important accomplishment if it holds true.

 

[FlameTail]

Ian Cutress posted a video about Dimensity 9300:

Dimensity 9300 uses 12-transistor SRAM cells for the L1 cache, whereas the industry norm is to to use 6-transistor SRAM cells for L1. Very interesting.

 

[Hesperax]

There seems to a bit discussion that either MediaTek or VIVO has used a Whitelist for Geekbench performance.

Results from a X200 Pro:

	Room Temperature	Refrigerator	Room Temperature + Renamed Geekbench Package	Refrigerator + Renamed Geekbench Package
Single-Core	2735	2910	2372	2772
Multi-Core	8507	9094	7776	8651

The X200 Pro only has 8533 MHz Memory.

The theory appears to be that the Whitelist allows Geekbench to:
1) Boost up to 3.8 GHz
2) Use 16KB Page Size

We probably need a more reputable source to analyze and confirm.

 

[DZero]

It seems that using their own core cache, helps a lot in the low powered big cores.

 

[FlameTail]

Dimensity 9300 flagship chip introduced the first all OoO CPU design for Android phones. Dimensity 9400 is the 2nd generation and follows on the heels of it's predecessor.

The next step should be to bring the all OoO design to midrange SoCs.

 

[MS_AT]

Initial results from gsmarena https://m.gsmarena.com/vivo_x200_pro_handson-review-2756p2.php

2675 Single Core GB6 (they dont specify subversion) but they note :

In fact, vivo promises even higher results, but since our unit is running a pre-production software, we will have to re-test once we have more time to spend with the X200 Pro, so stay tuned for the full review.

 

[DZero]

Dimensity 9300 flagship chip introduced the first all OoO CPU design for Android phones. Dimensity 9400 is the 2nd generation and follows on the heels of it's predecessor.

The next step should be to bring the all OoO design to midrange SoCs.

Maybe D8400 will be the one?

Chromebook Rauru shows that MTK goes with OoO this time too.

 

[FlameTail]

(Speculation)

High End Laptop CPU ala Strix/X Elite

X925 (3 MB L2) @ 4.0 GHz × 2
X925 (2 MB L2) @ 3.6 GHz × 8
A725 (1 MB L2) @ 2.4 GHz × 4
32 MB L3
16 MB SLC
Total Cache = 74 MB

Mid End Laptop CPU ala LNL/X Plus

X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB

A CPU with stock ARM cores can be kitted out with crazy amounts of cache.

For comparison, the total caches of X Elite, M4 and Lunar Lake respectively are 42 MB, 28 MB and 34 MB.

*Total Cache = L2 + L2 + SLC

@naukkis It seems Qualcomm/Apple's simple L1/L2 two-tier CPU cache hierarchy is also more 'capacity efficient'.

	L2 per core	L3
X Elite Oryon	3 MB	None
M4 P-core	4 MB	None
M3 Max P-core	2.66 MB	None
Cortex X925	upto 3 MB	upto 32 MB

ARM's latest X925 core can be configured with as much L2-per-core as Qualcomm/Apple, but ARM's L2 is private to each core, whereas in Qualcomm/Apple designs it's shared among a cluster of cores. ARM also needs to have an L3 cache on top of that, which seems wasteful.

 

[SpudLobby]

(Speculation)

High End Laptop CPU ala Strix/X Elite

X925 (3 MB L2) @ 4.0 GHz × 2
X925 (2 MB L2) @ 3.6 GHz × 8
A725 (1 MB L2) @ 2.4 GHz × 4
32 MB L3
16 MB SLC
Total Cache = 74 MB

Mid End Laptop CPU ala LNL/X Plus

X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB

A CPU with stock ARM cores can be kitted out with crazy amounts of cache.

For comparison, the total caches of X Elite, M4 and Lunar Lake respectively are 42 MB, 28 MB and 34 MB.

*Total Cache = L2 + L2 + SLC

@naukkis It seems Qualcomm/Apple's simple L1/L2 two-tier CPU cache hierarchy is also more 'capacity efficient'.

As you know, I have been saying this for a while now.

	L2 per core	L3
X Elite Oryon	3 MB	None
M4 P-core	4 MB	None
M3 Max P-core	2.66 MB	None
Cortex X925	upto 3 MB	upto 32 MB

ARM's latest X925 core can be configured with as much L2-per-core as Qualcomm/Apple, but ARM's L2 is private to each core, whereas in Qualcomm/Apple designs it's shared among a cluster of cores. ARM also needs to have an L3 cache on top of that, which seems wasteful.

 

[DZero]

(Speculation)

High End Laptop CPU ala Strix/X Elite

X925 (3 MB L2) @ 4.0 GHz × 2
X925 (2 MB L2) @ 3.6 GHz × 8
A725 (1 MB L2) @ 2.4 GHz × 4
32 MB L3
16 MB SLC
Total Cache = 74 MB

Mid End Laptop CPU ala LNL/X Plus

X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB

A CPU with stock ARM cores can be kitted out with crazy amounts of cache.

For comparison, the total caches of X Elite, M4 and Lunar Lake respectively are 42 MB, 28 MB and 34 MB.

*Total Cache = L2 + L2 + SLC

@naukkis It seems Qualcomm/Apple's simple L1/L2 two-tier CPU cache hierarchy is also more 'capacity efficient'.

	L2 per core	L3
X Elite Oryon	3 MB	None
M4 P-core	4 MB	None
M3 Max P-core	2.66 MB	None
Cortex X925	upto 3 MB	upto 32 MB

ARM's latest X925 core can be configured with as much L2-per-core as Qualcomm/Apple, but ARM's L2 is private to each core, whereas in Qualcomm/Apple designs it's shared among a cluster of cores. ARM also needs to have an L3 cache on top of that, which seems wasteful.

How about a Low end Laptop with...

X925 (3 MB L2) @ 3.5 GHz × 1
A725 (2 MB L2) @ 3.2 GHz × 3
A725 (1 MB L2) @ 2.25 GHz × 4
12 MB L3
8 MB SLC
Total Cache = 33 MB

 

[SteinFG]

Mid End Laptop CPU ala LNL/X Plus

X925 (3 MB L2) @ 4.0 GHz × 1
X925 (2 MB L2) @ 3.6 GHz × 3
A725 (1 MB L2) @ 2.4 GHz × 4
16 MB L3
8 MB SLC
Total Cache = 37 MB

A CPU with stock ARM cores can be kitted out with crazy amounts of cache.

This would have large cache and 3nm-only cores. That's high-end laptop territory.
More realistic scenario would be to follow AMD or Intel in midrange (at laest with cache and node): 4nm and ~24MB.
So something like Dimensity 9300 but with 128-bit memory controller.

 

[FlameTail]

@DZero your dreams may have come true.

Rumour:

Dimensity 8400 will have 8 × A725 cores?

 

[FlameTail]

It's most likely not 8 of one kind of A725 cores, but a combination of performance A725 + efficiency A725 cores.

The performance A725 cores would have more cache and clock higher (~3 GHz), whereas the efficiency A725 cores would have less cache and lower clock speeds (~2 GHz).

So could be a 2+6 or 4+4 combination for the Dimensity 8400.

 

[DZero]

@DZero your dreams may have come true.

Rumour:
View attachment 110635
Dimensity 8400 will have 8 × A725 cores?

I expected that since SD 7 one will go with all OoO core design and if the situacion with ARM happens... Series 6 and 4 will happen the same with the config you mentioned. The issue? Cost might increase a little, but more the energy consumption.

Seems that the in-order core era is about to end.

And indeed... I expect some configs.

Potential 1:
4 x A725 - 3.2 Ghz - 4 MB L2 Cache
4 x A725 - 2.0 Ghz - 2 MB L2 Cache
L3 Cache - 12 MB


Potential 2:
2 x A725 - 3.6 Ghz - 4 MB L2 Cache
6 x A725 - 2.0 Ghz - 3 MB L2 Cache
L3 Cache - 8 MB

But the Potential 2 might end being the Dimensity 7400 if goes all OoO config

 

[FlameTail]

I expected that since SD 7 one will go with all OoO core design and if the situacion with ARM happens... Series 6 and 4 will happen the same with the config you mentioned. The issue? Cost might increase a little, but more the energy consumption.

Seems that the in-order core era is about to end.

And indeed... I expect some configs.

Potential 1:
4 x A725 - 3.2 Ghz - 4 MB L2 Cache
4 x A725 - 2.0 Ghz - 2 MB L2 Cache
L3 Cache - 12 MB


Potential 2:
2 x A725 - 3.6 Ghz - 4 MB L2 Cache
6 x A725 - 2.0 Ghz - 3 MB L2 Cache
L3 Cache - 8 MB

But the Potential 2 might end being the Dimensity 7400 if goes all OoO config

Ahem...

The maximum amount of L2 cache the Cortex A725 can be configured with is 1 MB.

Even Dimensity 9400 only has a total of 7 MB of L2 private caches across it's 8 cores.