Discussion Mediatek SoC thread

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DZero

Member
Jun 20, 2024
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Ahem...

The maximum amount of L2 cache the Cortex A725 can be configured with is 1 MB.

Even Dimensity 9400 only has a total of 7 MB of L2 private caches across it's 8 cores.
Is 1 MB per core or per cluster? If is per core, it fits since the A725 on the big cores only uses 1 MB and on the "small ones" just 512 kb.
If is per cluster, well, time to use the L3 cache then.
 

FlameTail

Diamond Member
Dec 15, 2021
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Is 1 MB per core or per cluster? If is per core, it fits since the A725 on the big cores only uses 1 MB and on the "small ones" just 512 kb.
If is per cluster, well, time to use the L3 cache then.
ARM cores cannot be put in a cluster with shared L2.

That's why Apple/Qualcomm's CPU is special.
 

MS_AT

Senior member
Jul 15, 2024
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Are you sure of that? The private (but coherent) L2 is mandatory IIRC.
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/Arm-v8-Architecture hopefully the link points to the correct place. https://docs.amd.com/viewer/attachment/dqE2tE0k~iMhpEDoQwXIKg/DH_fGSDkzyH4lTKZ0NNiBg
The Cortex-A53 MPCore processor’s L2 memory system size is 1 MB. It contains the L2 cache pipeline and all logic required to maintain memory coherence between the cores of the cluster.
Anyway there are up to 4 cores in the cluster. Unless there is something that evades me, I think it is fair to say the cores in the cluster share the L2 cache.

AMD/Xilinx Versal should be similar but with A72 cores. Versal Gen2 is using A78 cores and indeed has L2 private caches and then L3.
 

Nothingness

Diamond Member
Jul 3, 2013
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https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/Arm-v8-Architecture hopefully the link points to the correct place. https://docs.amd.com/viewer/attachment/dqE2tE0k~iMhpEDoQwXIKg/DH_fGSDkzyH4lTKZ0NNiBg

Anyway there are up to 4 cores in the cluster. Unless there is something that evades me, I think it is fair to say the cores in the cluster share the L2 cache.

AMD/Xilinx Versal should be similar but with A72 cores. Versal Gen2 is using A78 cores and indeed has L2 private caches and then L3.
Sorry I wasn't clear: I was talking about A72 not A53.
 
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