Discussion MI100 Arcturus Datacentre GPU BIOS spotted.

uzzi38

Platinum Member
Oct 16, 2019
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128CUs. 1334mhz boost clock, 32GB HBM2 (4096-bit bus) 200W TDP (likely board power as it's not a power target but rather the name of the BIOS itself).

Looks like a huge step up in efficiency vs Vega 20, which had half the shaders, higher boost clock (1800mhz vs 1334mhz), same memory interface and a 300W TDP. This does total 87TOPs, but chances are final clocks (and power draw) will be higher to compensate
 

GodisanAtheist

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Nov 16, 2006
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Been a lot of speculation around the web about the size of this chip with 2x the shaders of the Vega 20. Some people are speculating a 700mm2 monster, but if all other execution units and memory subsystems are the same size and only the shader count is increasing I've heard others speculate that this will come in below the reported 7nm+ reticle limit of 429mm2.
 

DisEnchantment

Golden Member
Mar 3, 2017
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The AMDGPU patches for this GPU were upstreamed so many months in advance yet it has not seen light of day. Started with Bridgman on Phoronix forums almost something like 9 months ago.

Besides the doubled SPs,
New VCN2.5
New SMU
Interesting bits on the driver side has been the decent amount of work around XGMI for this specific GPU.

I won't be surprised if it has lots of bits of the planned interconnect for the Next Gen GPU-CPU interconnect.
 
Reactions: Glo. and uzzi38

uzzi38

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Oct 16, 2019
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The AMDGPU patches for this GPU were upstreamed so many months in advance yet it has not seen light of day. Started with Bridgman on Phoronix forums almost something like 9 months ago.

Besides the doubled SPs,
New VCN2.5
New SMU
Interesting bits on the driver side has been the decent amount of work around XGMI for this specific GPU.

I won't be surprised if it has lots of bits of the planned interconnect for the Next Gen GPU-CPU interconnect.
I knew Arcturus was... uh... something of an interesting one, but I hadn't heard any specifics. But as for the bit in the xGMI, remember the RRA certification the other day that many tech rumour sites called Big Navi?

Arcturus ain't far away.
 

uzzi38

Platinum Member
Oct 16, 2019
2,698
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Been a lot of speculation around the web about the size of this chip with 2x the shaders of the Vega 20. Some people are speculating a 700mm2 monster, but if all other execution units and memory subsystems are the same size and only the shader count is increasing I've heard others speculate that this will come in below the reported 7nm+ reticle limit of 429mm2.
I hadn't heard about that reticle limit, but I'm 99% certain it's wrong. Partially because of Arcturus itself.
 

joesiv

Member
Mar 21, 2019
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I hadn't heard about that reticle limit, but I'm 99% certain it's wrong. Partially because of Arcturus itself.
It'd be interesting if they went with a multi-die solution. If rumors of arcturus are correct in that it's a compute only solution (no display out at all), perhaps it's feasible?

700nm in 7nm seems pretty aggressive, but who knows, I'm sure it'll be an expensive part, but it'll eat up a lot of AMD's 7nm wafers per month they are alloted. Who knows how many they intend to sell, it seems that buyers of this type of card would be the hyper scale/super computer market, and when they order, they tend to order a lot at a time, thousands
 

Mopetar

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Jan 31, 2011
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For what AMD and NVidia are able to charge for these types of cards, it seems as though they only need two or three good dies per wafer to break even on the cost. That makes it feasible to do those kind of monster dies, and given that we've been told that 7 nm has matured quite well as far as processes go and it seems like a reasonable move. There was an interview with an AMD engineer who said that the chiplet approach used with Zen could be applied to GPUs being used in the HPC market (it just wasn't good for gaming) so we may see that eventually, but I suspect that AMD is still just trying to get their footing and it may be a few more years before any such chiplet-based approach emerges.
 
Mar 11, 2004
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mGPU is already very feasible in HPC. As in multiple cards scale very well, and dual GPU cards do too (Apple even went that route on the Mac Pro). Nothing special even really needs to be done. Chances are the way they've gone with CPUs is what is needed to get gaming to perform similarly, where they need the I/O die to abstract the GPU chiplets so that the system sees it as a monolithic chip. Now that's not an easy task. But they don't even really need that for HPC stuff. Not saying it wouldn't benefit there (it likely would, especially if it enabled them to tune things like do more memory or go with faster memory, etc; it'd let them do some interesting stuff with HBM that probably wasn't feasible when trying to stack it right next to a huge GPU on an interposer that could fit all of that).

It'd be interesting if they went with a multi-die solution. If rumors of arcturus are correct in that it's a compute only solution (no display out at all), perhaps it's feasible?

700nm in 7nm seems pretty aggressive, but who knows, I'm sure it'll be an expensive part, but it'll eat up a lot of AMD's 7nm wafers per month they are alloted. Who knows how many they intend to sell, it seems that buyers of this type of card would be the hyper scale/super computer market, and when they order, they tend to order a lot at a time, thousands

From what I've gathered they could pretty easily do multi-chip/dice for non-gaming markets as those tend to scale quite linearly (think it was like only around 4th card that they started to see much dropoff and even then it was still quite high, like 80%+ on the 4th card). I've thought that "big Navi" might be a multi-chip solution. I think they could even simplify things further, by making the memory a separate thing itself (so put an I/O die on the interposer with stacks of HBM, simplifying HBM and GPU in one fell swoop). And that would potentially be helpful for gaming as well.
 
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