Need help understanding how DDR2/3/4 Memory works

[TheDarkKnight]

I've been reading a lot about how DDR2/3 memory works. It's fascinating stuff. But some of the articles don't go into enough detail for me I guess.

Let's talk about a few characteristics of DDR3 for this discussion. I find the following stats on this Wikipedia article:

https://en.wikipedia.org/wiki/DDR3_SDRAM

It shows that every "standard name" DDR3 I/O bus clock is a multiple of 4 times the memory clock speed.

So, for example, DDR3-1600 runs at a memory clock speed of 200MHz and therefore the I/O bus clock runs at 4x 200MHz for an I/O bus clock speed of 800MHz.

My question is....what is this magic multiplier of 4. I've almost got this all down except for this part I think.

Is the I/O bus clock the "bridge" on the actual motherboard that connects the memory to the CPU? And is this bus transferring data at a rate of 4x faster because of the data literally moving 4x faster over a single lane(so to speak) or are there 4 lanes on the I/O bus clock?

Hope someone understands this just a little bit better than I do. Thanks for reading.

 

[bradly1101]

Someone correct me if I'm wrong, but I think it gets to 2x by transferring data on the upswing and downswing of the voltage change representing a one or zero, and the other 2x comes from running in parallel.

 

[Elixer]

You want details?
http://www.jedec.org/standards-documents/docs/jesd-79-3d
Try not to fall asleep reading all that.

 

[TheDarkKnight]

You want details?
http://www.jedec.org/standards-documents/docs/jesd-79-3d
Try not to fall asleep reading all that.

Ultimately, what I want is ... understanding. But I'll take a deep breath and wade into the deep waters you have alluded to. *big deep breath*.

Still, if anyone can explain it to me like I'm a dummy that works also.

 

[TheDarkKnight]

Someone correct me if I'm wrong, but I think it gets to 2x by transferring data on the upswing and downswing of the voltage change representing a one or zero, and the other 2x comes from running in parallel.

I think along the same lines. I am not exactly sure what you mean by "running in parallel". We are not yet even talking about running your system memory in dual-channel memory mode. If the actual internal transfer lines of the internal memory bus doubled or quadrupled then that might clear things up a bit.

I am wondering if the jump from the memory clock of 200MHz to the I/O bus clock of 800MHz is just a "theoretical" or "effective" measurement of MHz versus actual. But then I say, no, it's actual. The FSB that connect the memory channels to the CPU itself actually(I believe) runs at 800MHz.

So, the first multiplier of 2x on the base memory clock of 200MHz for DDR I understand. I think maybe the second multiplier of 2x comes from the fact that DDR3 doubled the data-chunk size from 4-bits to 8-bits. So, I think that's why the I/O bus clock has to run at 800MHz.

It's still all a little fuzzy but I'm getting there.

 

[greenhawk]

I have to go from memory here.

It is easier to work out what each version does if you know what the one before did.

Before DDR, the information on the data lines changed only once per cycle (up and down) of the clock single line.

when DDR came in, the clock speed was about the same, but the DDR (Double Data Rate) started to use the upwards and downwards change of the signal on the clock line. So while you had a clock speed of say 200Mhz (I can not remember the actual numbers), data moved as if you had a 400MHz clock speed.

When DDR2 came out, it brought with it far far smarter logic / circuits that "guessed" where the middle was between the up and downwards movement of the clock signal. And so also the middle between the downwards and upwards movement. This meant that the data on the clock signal line might be running at 200Mhz, but the amount of information pushed through the data lines became 4x as much, so effectively 800Mhz. If you can not tell, this is partly where the numbering system for the ram is worked out (ie: DDR2-800 ect).

DDR3 as the wiki link in the original post mentiones, is that they doubled the data again from DDR2, so instead of sending data on the up/down of the clock signal, the circuity is now splitting each half cycle (half the time high, half the time low) up in to 4, so that the information on the data lines is changing 8 times for each full change / cycle of the clock.

Not 100% sure what DDR4 is doing, but a look at the wiki page indicates the base clock speed has been changed. DDR3 was 100Mhz to 266Mhz base, to DDR4 which is 800Mhz to 1200Mhz base.

edit: And just to be sure you do not get confused, GDDR has no relation to DDR IIRC, they use similar numbers to mean something completely different.

 

[greenhawk]

If you want to get into a bit more nitty gritty, then you will have to look into why DDR2 and the later ones where developed.

When moving data from one point to another, the easiest way to increase the amount of information that arrives is to increase the number of wires being used. This works when going from 1 to 2, 2 to 4, 4 to 8, but it starts to get very silly when you start looking at going from 32 to 64, 64 to 128 ect. The biggest issues with this is space. running all those wires gets tricky, then you have issues with getting all those wires (and supporting wires like control lines and clocks ect) into devices/chips at both ends. This requires legs/pins/connectors, and the more of them you have, the harder it is to route the wires and the increase in costs to manufacture. Side note: it is this cost to manufacture as to why we have dual and quad channel memory, as using multiple of a common part (ram stick) is cheaper than creating a new and bigger memory component.

So the next step is to speed up the signals, so more is moving over a given time period, which is where DDR started. This is partly due to issues with timing. As the faster you make a signal go, the harder it is to ensure that all wires at the same length and so a signal sent is "seen" the same at the other end. This is one of the reasons a clock is best kept as slow as possible.

The ideal world then is to have one or two very very high speed signals that do not care about any other wires or singles, which is the idea behind where sata (HDD/SSD) comes from. Instead of running a set of wires at several hundred Mhz, you can run a single wire at several Gigabits/s.

This approach for not caring when the data arrives (vs other wires) is also the backing on why we have PCI express. That is the serial replacement of the older PCI slot (which was 32bit wide shared data bus). There was some attempts at going faster with PCI with 64 bit version of the slots, and also doubling the clock speeds, but due to costs these where mainly only seen on server grade boards. Note: if you want to go back to before PCI, you have ISA, both in 16 and 8 bit formats

PCI Express was also a advancement on video cards as they went from PCI (and another one called VESA IIRC) to one called AGP which speed up over time from x1 speeds (basically a dedicated PCI IIRC) to x8 speeds (vs the older PCI slot IIRC, it has been too long).

But I digress.

The question some ask here is why did all these other parts of a PC go serial for speed when a main and always used thing like memory did not?

For that you need to go back to the start of the intel P4 era and look at the untalked about ram called RAMBUS. That was a serial memory, but due to some trickery and lies (or so the story goes as there were many many lawyers involved for years), they ended up with the patent for the RAMBUS memory and so wanted royalties from all ram and motherboard makers. And it was a highway robbery level prices. Enough to nearly kill off the PC, if not several manufactures.

This RAMBUS was meant to be the replacement for the SD memory of the time. But the court cases, the royalties and the need for the manufactures to have something to sell, DDR was rushed to market (not sure if they had it in the wings ready go or what) as it was a very quick (year?) turn around.

And so, while the case ran, the industry moved to DDR and on-wards.


On a side note: it is this last minute change of memory which made the Pentium 4's such a joke of a CPU. It was designed for the fast access time of RAMBUS and that design did not work with SD/DDR very well at all, especially when the cpu needed translation logic to convert the data coming from the memory (that was in parallel) and to change it into the serial format the CPU was expecting. Doing this both ways added huge time delays to memory and so slowed down effective speed of the CPU something shocking. Even my poor student status at the time got to play on a P4 with rambus and it was FAST. the 1.6Ghz with I think 128MB ram stomped all over the P4 2.4Ghz unit with 512MB (or so IIRC) of DDR. Response time was as different as a SSD vs HDD computer system (I probably exaggerate but it floored me at the time).


I am not sure just how much the memory issue played into it, but when intel gave up on the P4 design and replaced it with something better, so was born the original core processor. It did not make a huge splash as I recall until version 2 came out, and it was a monster