Nehalem: AMD's design!

[Philippart]

http://www.anandtech.com/weblo...st.aspx?i=480#comments

 

[SlowSpyder]

I'm pretty sure Nehalem is Intel's design.

 

[aigomorla]

Originally posted by: SlowSpyder
I'm pretty sure Nehalem is Intel's design.

lol..

i think what he's trying to say is like how SLI is really 3dFX's idea, but nvidia only expanded on it.

 

[SunnyD]

QPI = Hypertransport
IMC = Athlon 64
On Die Core-to-Core crossbar = Athlon 64 X2 & (Phenom).
Upcoming on die GPU = Fusion

The only catch is that it's Intel's spin on AMD's success.

 

[OCGuy]

Where did AMD get its first microprocessor designs?


No but serioulsy we should all buy Deneb even though it will be 12-18 months behind because Intel is using IMC on i7.

 

[Markfw]

Originally posted by: Ocguy31
Where did AMD get its first microprocessor designs?


No but serioulsy we should all buy Deneb even though it will be 12-18 months behind because Intel is using IMC on i7.

Didn't IBM start all this actually with the 8088 ?

IBM PC
IBM PC AT (286)
and so on ?

 

[error8]

So what if it's AMD design? Intel took what was good from AMD and further improved it. I don't see anything wrong here, just some very fast cpus that are about to be born. I can't wait.

 

[dmens]

Originally posted by: SunnyD
QPI = Hypertransport
IMC = Athlon 64
On Die Core-to-Core crossbar = Athlon 64 X2 & (Phenom).
Upcoming on die GPU = Fusion

The only catch is that it's Intel's spin on AMD's success.

LOL if only you knew how different CSI is from HT, or the IMC, or the way the requests are handled. Shit like that makes me laugh.

According to your logic, K7 = P6.

 

[SunnyD]

Originally posted by: dmens

Originally posted by: SunnyD
QPI = Hypertransport
IMC = Athlon 64
On Die Core-to-Core crossbar = Athlon 64 X2 & (Phenom).
Upcoming on die GPU = Fusion

The only catch is that it's Intel's spin on AMD's success.

LOL if only you knew how different CSI is from HT, or the IMC, or the way the requests are handled. Shit like that makes me laugh.

According to your logic, K7 = P6.

Funny... a serial point-to-point interconnect no matter how you dice it is essentially the same thing. Just because the command set is labeled differently doesn't make them completely different technologically. Since both are derived from the EV7 bus, I guess both AMD and Intel both are taking a spin on DEC's ... uh ... success?

And no, K7 != P6. K7 ~ P5, just as Core ~ P5. The P6, well... that was something mostly different architecturally... the only thing it shared with the P5 was the instruction set, and the instruction set does not the architecture make (Re: Itanium's x86 compatibility, but radically different architecture).

 

[Fox5]

Originally posted by: dmens

Originally posted by: SunnyD
QPI = Hypertransport
IMC = Athlon 64
On Die Core-to-Core crossbar = Athlon 64 X2 & (Phenom).
Upcoming on die GPU = Fusion

The only catch is that it's Intel's spin on AMD's success.

LOL if only you knew how different CSI is from HT, or the IMC, or the way the requests are handled. Shit like that makes me laugh.

According to your logic, K7 = P6.

How different? CSI seems like it is better.

 

[solog]

Originally posted by: Markfw900

Originally posted by: Ocguy31
Where did AMD get its first microprocessor designs?


No but serioulsy we should all buy Deneb even though it will be 12-18 months behind because Intel is using IMC on i7.

Didn't IBM start all this actually with the 8088 ?

IBM PC
IBM PC AT (286)
and so on ?

Intel made the 8088. How did you ever become a CPU mod?

Keep the moderator comments to yourself please. Stick to the topic and do not
insult anyone. Thank you.

Anandtech Moderator - Keysplayr2003

 

[SunnyD]

Originally posted by: solog

Originally posted by: Markfw900

Originally posted by: Ocguy31
Where did AMD get its first microprocessor designs?


No but serioulsy we should all buy Deneb even though it will be 12-18 months behind because Intel is using IMC on i7.

Didn't IBM start all this actually with the 8088 ?

IBM PC
IBM PC AT (286)
and so on ?

Intel made the 8088. How did you ever become a CPU mod?

Oh snap!

 

[dmens]

Originally posted by: SunnyD

Originally posted by: dmens
LOL if only you knew how different CSI is from HT, or the IMC, or the way the requests are handled. Shit like that makes me laugh.

According to your logic, K7 = P6.

Funny... a serial point-to-point interconnect no matter how you dice it is essentially the same thing. Just because the command set is labeled differently doesn't make them completely different technologically. Since both are derived from the EV7 bus, I guess both AMD and Intel both are taking a spin on DEC's ... uh ... success?

And no, K7 != P6. K7 ~ P5, just as Core ~ P5. The P6, well... that was something mostly different architecturally... the only thing it shared with the P5 was the instruction set, and the instruction set does not the architecture make (Re: Itanium's x86 compatibility, but radically different architecture).

it's the same thing only in the sense that they are both interconnects and it stops right there. that is why i compared your reasoning to k7 = p6. because they are both cpu's. i could have said, k8 = p4 as well and it would have been about as accurate.

core ~ p6 you mean, and k7 has nothing in common with p5. p5 is in-order. k7 is out-of-order just like p6, and the microcode was awfully similar...

 

[SunnyD]

Originally posted by: dmens

Originally posted by: SunnyD

Originally posted by: dmens
LOL if only you knew how different CSI is from HT, or the IMC, or the way the requests are handled. Shit like that makes me laugh.

According to your logic, K7 = P6.

Funny... a serial point-to-point interconnect no matter how you dice it is essentially the same thing. Just because the command set is labeled differently doesn't make them completely different technologically. Since both are derived from the EV7 bus, I guess both AMD and Intel both are taking a spin on DEC's ... uh ... success?

And no, K7 != P6. K7 ~ P5, just as Core ~ P5. The P6, well... that was something mostly different architecturally... the only thing it shared with the P5 was the instruction set, and the instruction set does not the architecture make (Re: Itanium's x86 compatibility, but radically different architecture).

it's the same thing only in the sense that they are both interconnects and it stops right there. that is why i compared your reasoning to k7 = p6. because they are both cpu's. i could have said, k8 = p4 as well and it would have been about as accurate.

core ~ p6 you mean, and k7 has nothing in common with p5. p5 is in-order. k7 is out-of-order just like p6, and the microcode was awfully similar...

You seem to lack reading comprehension skills.

HT & QPI - Both high speed serial point-to-point interconnects. Who cares if one uses a positive signal and one uses a negative signal, or a fetch command on one is called "A" and on the other is "B". Other than very minor variations, both are effectively the same technologies.

And no, I mean Core ~ P5. The architecture of a Core CPU is derived from the Pentium M, which is derived from the P5. The P6 microarchitecture is vastly different from the P5 and Core series.

I do apologize somewhat on the K7. It's x86 family lineage derives from the last licensed x86 product AMD had from Intel which was the P5. The actual architecture however derives from both Next's Nx586 and the DEC Alpha. I suppose in retrospect I should have realized this one. But it doesn't change a damn thing about QPI versus HT.

 

[Markfw]

Originally posted by: solog

Originally posted by: Markfw900

Originally posted by: Ocguy31
Where did AMD get its first microprocessor designs?


No but serioulsy we should all buy Deneb even though it will be 12-18 months behind because Intel is using IMC on i7.

Didn't IBM start all this actually with the 8088 ?

IBM PC
IBM PC AT (286)
and so on ?

Intel made the 8088. How did you ever become a CPU mod?

What does my knowledge of who made the 8088 have to do with me being a mod ? I never researched that, and it was a question anyway.

And I was elected by everyone here. Also, we don't like insulting people on this forum.

 

[dmens]

Originally posted by: SunnyD
You seem to lack reading comprehension skills.

HT & QPI - Both high speed serial point-to-point interconnects. Who cares if one uses a positive signal and one uses a negative signal, or a fetch command on one is called "A" and on the other is "B". Other than very minor variations, both are effectively the same technologies.

And no, I mean Core ~ P5. The architecture of a Core CPU is derived from the Pentium M, which is derived from the P5. The P6 microarchitecture is vastly different from the P5 and Core series.

I do apologize somewhat on the K7. It's x86 family lineage derives from the last licensed x86 product AMD had from Intel which was the P5. The actual architecture however derives from both Next's Nx586 and the DEC Alpha. I suppose in retrospect I should have realized this one. But it doesn't change a damn thing about QPI versus HT.

so ultimate purpose overrides underlying technology. that's good. therefore:

- model T = veyron, A to B
- sopwith camel = f22 raptor, A to B and shoots down planes!
- 8088 = nehalem, both process x86 instructions

i hope you meant by minor variations, you meant that HT and CSI and way different in their layers, protocols, training, etc. read the RWT overview of CSI technology.

pentium M has nothing to do with P5 and everything to do with P6. go look it up.

funny how you insist K7 derives from 3 different in-order architectures, one of which is not even x86. for crying out loud, do your research.

 

[Roy2001]

Originally posted by: SunnyD
QPI = Hypertransport
IMC = Athlon 64
On Die Core-to-Core crossbar = Athlon 64 X2 & (Phenom).
Upcoming on die GPU = Fusion

The only catch is that it's Intel's spin on AMD's success.

Seems the last thing AMD and AMD fanbois can do is to put out this kind of BS. What else?

 

[OCGuy]

Originally posted by: Roy2001

Originally posted by: SunnyD
QPI = Hypertransport
IMC = Athlon 64
On Die Core-to-Core crossbar = Athlon 64 X2 & (Phenom).
Upcoming on die GPU = Fusion

The only catch is that it's Intel's spin on AMD's success.

Seems the last thing AMD and AMD fanbois can do is to put out this kind of BS. What else?

They will conveniently forget about Penryn and Yorkie when Nehalem doesnt bring huge gains in gaming, (although Im not sure what a better CPU could do for my games right now) and recommend Deneb, even though early benches show Deneb behind Intels current lineup. And I doubt AMD will be offering anything near the chip in my sig for a while. Maybe Bulldozer? We'll see.

 

[SunnyD]

Originally posted by: dmens

Originally posted by: SunnyD
You seem to lack reading comprehension skills.

HT & QPI - Both high speed serial point-to-point interconnects. Who cares if one uses a positive signal and one uses a negative signal, or a fetch command on one is called "A" and on the other is "B". Other than very minor variations, both are effectively the same technologies.

And no, I mean Core ~ P5. The architecture of a Core CPU is derived from the Pentium M, which is derived from the P5. The P6 microarchitecture is vastly different from the P5 and Core series.

I do apologize somewhat on the K7. It's x86 family lineage derives from the last licensed x86 product AMD had from Intel which was the P5. The actual architecture however derives from both Next's Nx586 and the DEC Alpha. I suppose in retrospect I should have realized this one. But it doesn't change a damn thing about QPI versus HT.

so ultimate purpose overrides underlying technology. that's good. therefore:

- model T = veyron, A to B
- sopwith camel = f22 raptor, A to B and shoots down planes!
- 8088 = nehalem, both process x86 instructions

i hope you meant by minor variations, you meant that HT and CSI and way different in their layers, protocols, training, etc. read the RWT overview of CSI technology.

pentium M has nothing to do with P5 and everything to do with P6. go look it up.

funny how you insist K7 derives from 3 different in-order architectures, one of which is not even x86. for crying out loud, do your research.

For the last time - QPI and HT both are Point-to-Point High Speed Serial Interconnects. QPI and HT are technologically equivalent, where as QPI/HT are NOT the same at GTL+/FSB. They do the same thing, in the same manner. It doesn't matter if the protocol stack is any different, from an architectural standpoint they are just about identical.

 

[pm]

So then gigabit Ethernet - which is also a high-speed serial point-to-point SerDes design - is the same thing as HT as well?

 

[dmens]

Originally posted by: SunnyD
For the last time - QPI and HT both are Point-to-Point High Speed Serial Interconnects. QPI and HT are technologically equivalent, where as QPI/HT are NOT the same at GTL+/FSB. They do the same thing, in the same manner. It doesn't matter if the protocol stack is any different, from an architectural standpoint they are just about identical.

CSI and HT are not technologically equivalent because they do sorta the same thing in different ways, then CSI does a bunch more stuff as well.

your original post asserted intel copied amd interconnect, IMC and the crossbar. there's nothing in common at all with those three items, so stop trying to argue the point.

 

[pm]

The i386SL had an integrated memory controller.
The IBM Power4 had a CPU-to-CPU on-die switched fabric crossbar in 2001.

 

[Sohcan]

Originally posted by: pm
The i386SL had an integrated memory controller.
The IBM Power4 had a CPU-to-CPU on-die switched fabric crossbar in 2001.

Hell, the nCUBE/2 had an integrated DRAM controller and I/O fabric (with 14 links supporting up to 8096 processors)...in 1991. And as far as core microarchitectures, most of the really exciting stuff was established in IBM's mainframes in the 60s.

Honestly, there's not much architecturely new that has come out of the industry in the last 15 years...just stuff that was developed in mainframes and supercomputers from the 60s through early 90s that has simply taken time to filter down into mainstream microprocessors through increased integration.

 

[Idontcare]

Originally posted by: pm
So then gigabit Ethernet - which is also a high-speed serial point-to-point SerDes design - is the same thing as HT as well?

No dude, you are so wrong, what magazine did you get your EE degree from?

Clearly there is nothing deeper, nothing more sophisticated about the fundamental design and implementation of these systems beyond just the fancy catch phrases that we read about. SunnyD is right, way way right.

QPI is soooo obviously nothing more than AMD's HT. Transistor for transistor, interconnect trace for interconnect trace, identical to 7-9's.

I've seen all the cartoon drawings of the system components on the interwebz and they clearly show QPI is a colored line connecting 2 or more CPU's, same as the colored bar I see called HT connecting AMD CPU's. It couldn't be any less complicated of a thing for Intel to steal from AMD.

So how dare you insinuate or imply that just because things get 2 and 3 letter acronyms and show up at the same place in cartoony single-slide graphics that there is anything deeper or more fundamental to getting the job done such that there might actually be a differentiation in the technology and innovation.

For shame.



(I know pm will get the sarcasm, but for anyone reading this post and thinking I am serious please realize this is sarcasm at its worst)

 

[Meph3961]

Originally posted by: SunnyD
And no, I mean Core ~ P5. The architecture of a Core CPU is derived from the Pentium M, which is derived from the P5. The P6 microarchitecture is vastly different from the P5 and Core series.

You are correct on two points. First the Core Microarchitecture is derived from the Pentium M and that the P6 is vastly different from the P5. But how in the world do you think that the Core Microarchitecture is derived from the P5 and not the P6 eludes me. The P6 brought us speculative execution and out of order completion, superpipelining (taking the P5's 5 stage pipeling to 14 stages for the P6, which is roughly how long Core's pipeline is), register renaming, and an integrated L2 cache. All of which are used in the Core Microarchitecture. The biggest difference between the P5 and Core is that the P5 was an in-order processor and every thing from Intel since the P6 has been out-of-order.

Maybe you are getting Larrabee and Core confused (I don't know how). Larrabee does use cores based on the P5 with some modifications.