QPI and HT are similar technologies in the sense that they are both point-to-point high speed serial interconnects. Because they provide near identical benefits, you could say Intel stole one out of AMD's playbook. The truth of the matter is, AMD probably wishes Intel would've used HT instead of their proprietary redesign. Though they are very similar technologies at a high level, the architectural details are different. Each was developed for a similar but different purpose.
Something to keep in mind:
AMD doesn't own HT (originally named LDT). They are part of a group that developed the technology as a standard interconnect technology for many types of devices. Because of this, HT was designed to work well as both CPU interconnects and I/O interconnects. If Intel were to adopt HT (at least for I/O), chipset manufacturers would need only make a single chipset for both AMD and Intel processor. You'd still have different sockets, but it is conceivable that you could use Intel chipsets for AMD processors and vice versa. (Hybrid systems with both Intel and AMD processors might be possible as well, but it would be hard or impossible to make them cooperate efficiently if at all).
Intel, on the other hand, developed QPI, first and foremost, to speed up its CPU to CPU communications. I/O connectivity seems like a secondary consideration and is left to the third party developer. (as in ambiguous and non-standardized or more flexible to put a different spin on it)
What I consider the largest advantage of CSI over HT has a downside. The advantage is that by bypassing the arbiter initially and making read requests directly to the peers, they can achieve lower latency (on average) peer to peer communications. This method is risky, but Intel has built in the necessary circuitry to stop any flawed transactions. I/O devices, however, seem to favor the arbiter system, thus a bridge chip, with a fairly sophisticated design if you want to preserve QPI's lower latency, becomes necessary. HT's ability to lane split combined with their arbiter system gives it the ability to directly connect I/O devices to the CPU, assuming HT interconnects. I'm not really sure if QPI supports lane splitting, but it is harder for I/O devices to support its communication scheme directly. Connection speed can always be increased with the version of the technology, so I don't really see this as an advantage for either. However, if backwards compatibility is required, you'd have to stick with the communications scheme of the previous version. (Hence, latency wouldn't change)
I can't see a the additional latency of a bridge chips affecting most I/O devices, since they are, relatively speaking, slow anyway. So overall, I think Intel made a good trade-off. However, if AMD can get partners to bring HT connected GPU (desktop/workstation) or HT bridged high speed external devices in which lower latency is desirable (think higher speed fibre-channel, Serial rapid I/O, etc.) to the market, then they may be able to claim an advantage. Unfortunately for AMD, video cards are currently designed to hide the extra latency associated with bridged connectivity. Also, outside of special purpose high speed data recoding systems, I can't think of many applications that would require a low latency external connection.
My understanding of QPI is incomplete, but my points should still be valid. I'll read more in depth about it when I have both the time and proper documents.