Originally posted by: Viditor
I am not positive...but I believe it to be true (I have been looking for confirmation either way, but to no avail as of yet).
The last I heard there will be 4 different sockets, with/without QPI and with/without IMC.
It would be pretty amazing if true as that would mean Nehalem cache hiearchy (L1/L2/L3) is either redesigned for the non-IMC version or the Nehalem cache hiearchy is crazy robust and can take such widely varying RAM access times (quick w/IMC versus delayed w/o IMC) and manage to not totally bottleneck the CPU.
In other words, if Nehalem's performance is not dependent on the IMC then shame on Intel for wasting shareholder profits by reducing GM's and needlessly including the IMC on the Nehalem.
If Nehalem's performance is dependent on the IMC then shame on Intel for wasting shareholder profits by increasing up-front R&D design expenses in creating a needless Nehalem SKU for a market condition where a Penryn could have readily been fielded.