New Core i7 Stepping "D0" set to launch?

[ghost recon88]

Originally posted by: aigomorla

Originally posted by: TuxDave

Originally posted by: aigomorla
waiting to throw my unlocked B0's on a DP QPI overclockable board.

B0 hmmm? Well I guess we did manage to get the memory controller running at the right speed on that stepping. You can all thank me later.

http://i125.photobucket.com/al...igomorla/Capture-1.jpg



The 920 i was playing with and the 965 is C0/C1

What board have you tried it in? I heard the Asus P6T Deluxe worked with the B0 chips that were multi unlocked (aka the 940XE). I haven't personally used the Asus P6T Deluxe though.

 

[RMSe17]

how do you all get them..?!

 

[aigomorla]

Originally posted by: ghost recon88

Originally posted by: aigomorla

Originally posted by: TuxDave

Originally posted by: aigomorla
waiting to throw my unlocked B0's on a DP QPI overclockable board.

B0 hmmm? Well I guess we did manage to get the memory controller running at the right speed on that stepping. You can all thank me later.

http://i125.photobucket.com/al...igomorla/Capture-1.jpg



The 920 i was playing with and the 965 is C0/C1

What board have you tried it in? I heard the Asus P6T Deluxe worked with the B0 chips that were multi unlocked (aka the 940XE). I haven't personally used the Asus P6T Deluxe though.

Yeah, so does the Giggys and the SO's

Problem with Single Processor boards and gainestown was i think the overclocking QPI is on the disabled QPI bus on that cpu.

Since gainestown is 2x qpi and i7 is 1x qpi, one of my qpi bridges is disabled on the board side. This also killed about 3 overclocking options.

http://i125.photobucket.com/al...aigomorla/IMG_0162.jpg

See im missing unclk and one other option at the bottom.

Which is why i need a 2x qpi DP overclocking board.

Okey one of you Intel TECH guys. Look at this:
http://www.xtremesystems.org/f...3618532&postcount=2553

According to that chart: (and please correct me if im wrong)

Safe max Vcore is 1.55?
Safe Max VTT is 1.35?
And safe QPI/Dram Voltage is 1.35?
And safe PLL is 1.875?

if your not on water i wouldnt push it higher then 1.4, you'll see how hot these girls get.

But can one of you intel tech guys double confirm please? That vcore honestly scares the crap out of me.

 

[Diogenes2]

.....Of course they had too cool the CPU with LN2....

'Nuff said ....

 

[dmens]

Originally posted by: aigomorla
Okey one of you Intel TECH guys. Look at this:
http://www.xtremesystems.org/f...3618532&postcount=2553

According to that chart: (and please correct me if im wrong)

Safe max Vcore is 1.55?
Safe Max VTT is 1.35?
And safe QPI/Dram Voltage is 1.35?
And safe PLL is 1.875?

if your not on water i wouldnt push it higher then 1.4, you'll see how hot these girls get.

But can one of you intel tech guys double confirm please? That vcore honestly scares the crap out of me.

ive gone higher on an engineering setup, but that was with a cooling setup that costs more than my house and a power supply that can probably light up my house. at those voltages you can expect the part to die very quickly.

 

[Idontcare]

Originally posted by: dmens
ive gone higher on an engineering setup, but that was with a cooling setup that costs more than my house and a power supply that can probably light up my house. at those voltages you can expect the part to die very quickly.

C'mon now dmens, I mean we all know Intel's stock HSF costs more than your Maytag Fridge cardboard box of a house...your not telling us anything new here

Seriously though what purpose (if you can tell us) does running these tests satisfy? I'm familiar with the standard elevated voltage/temperature test conditions for accelerated lifetime testing, but it sounds like in your case it is being done just to see what is limiting the clockspeed regardless of lifetime?

 

[Denithor]

Waiting for Westmere...

 

[exar333]

Any reports of better overclocks and/or cooler temps with the D0 stepping? If it was significantly better, I might make the switch. Otherwise, I am too waiting for Westmere....

 

[nyker96]

so what is "better' about this D0? higher OC headroom?

 

[dmens]

Originally posted by: Idontcare
Seriously though what purpose (if you can tell us) does running these tests satisfy? I'm familiar with the standard elevated voltage/temperature test conditions for accelerated lifetime testing, but it sounds like in your case it is being done just to see what is limiting the clockspeed regardless of lifetime?

yeah i wanted to see where the wall was. this was with a tester, not a computing setup.

 

[Idontcare]

Originally posted by: dmens

Originally posted by: Idontcare
Seriously though what purpose (if you can tell us) does running these tests satisfy? I'm familiar with the standard elevated voltage/temperature test conditions for accelerated lifetime testing, but it sounds like in your case it is being done just to see what is limiting the clockspeed regardless of lifetime?

yeah i wanted to see where the wall was. this was with a tester, not a computing setup.

Awesome. I love the fact your employer empowers you with the right equipment and time/rope to run these kinds of tests. Even if they aren't fully reviewed/sanctioned tests as part of a larger organized internal study or project, the fact they don't go out of their way to stand in your way is pretty cool.

So what's the gut-perspective on HK/MG, does it enable you to go places with the design/clockspeed you simply could not have gone otherwise or is it more of a nice thing to have as it finely gets rid of some headache restrictions that were hobbling innovation at the architecture/design/layout level? (asking for just your personal perspective, not your employer's, if you are comfortable discussing it even under such pretense)

SUN always gave us the strong impression HK/MG was a nice to have, but not a need to have. Meaning they didn't feel the spice-models and xtor device physics of traditional doped-poly gates and plasma nitrided gate oxide were a critically limiting factor in their IC designs. We had HK ready for deploy since 90nm but they never wanted it (cost factor) so we never went to production with it, I suspect this is the case with nearly all the major IDM's as our benchmarking results usually concluded as much. Although I must admit Intel was absolutely never on our radar as being a contender for deploying HK/MG at 45nm. Total surprise.