itsmydamnation
Platinum Member
- Feb 6, 2011
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And how, precisely, are they going to do cache coherence over Seamicro fabric?
There not its called GMI, the current rumor/piece together of patients and linked in profiles is distributed memory controllers (2 channels on each die) connected over impossor. Impossor can handle lots of wires at high speeds and require little power, we know from some of the latest digging by dresdenboy that AMD's L3 write policy is locality aware, which you would want for such a setup.