The EDA (IC Compilers and Validators) for the 14nm LPP includes all the libraries for the process, but it is the designers that will choose to use or not the M1 double Patterning for Highest Density and performance.
You're wouldn't be the first but I'm seeing people here routinely confusing these concepts and treating them as if they are one and the same.
Design automated tools, and their capabilities or limitations are something completely different to the base process. The tools are provided by the likes of Synopsys, Cadence, etc. They are for IC design, analysis and verification like you state. As in mostly automated software rather than manual.
Chip architectural tweaks are also different and independent to logic level and circuit level tweaks.
DP is something I'm not sure is even relevant in this context, today. It's a litho RET technique though. As in, allowing better optical focusing for small features and edges. Using it creates complexity... limitations to the chip design, performance and variability (like misalignment between critical layers) tho.
In terms of libraries, High Density and High Performance don't coexist for an IC. There is no jack of all tricks here. HD is rarely even used across all the chip, just certain sections... except when the primary focus is as a LP SoCs.
It would be great to see how AMD ends up tackling this common compromise. Sam, Mike and Jim's words are clear: you usually have to make a choice, a balance, in these 3 main aspects of power, performance and size. They've said this time, they've tried the best of three approach, and they've said this incurs a huge risk no one wants to take. The risk being, trying for all 3 can end up with a chip that has multiple domain issues on all 3 fronts, or a serious issue on any one front.
With their advances and improvements in process tech, as a single design, we know AMD can:
1. Make XV+20% performance.
2. Make XV<20% power.
3. Make Bulldozer<20% frequencies.
PPF
With this chip, my understanding is that they've tried to hit a middle ground of all, with a focus on IPC.
“I think of Zen as balance,” Mike Clark, the senior fellow and lead architect at AMD who steered the design of the Zen core, explained in rolling out its design. “And I think of my job as an architect as trying to balance all of the competing forces. You are given a transistor allocation, and you want to use the transistors as best you can and build the best core you can. But there are the competing interests of clock frequency, how much work you can get done per clock, the power, the complexity of the ISA, which you have to get functionally correct and new instructions you might want to add. We were working on the Bulldozer line, and we were improving with the Excavator core, learning, but we could see that we needed to make some bigger changes. If you try to make a big change in the architecture, however, it really throws off the balance. You realize you need to rebalance everything and do a grounds-up core. We set a goal of getting 40 percent more instructions per clock while keeping the other forces at bay, and set a new point for the architecture that we could build on going forward.”
“Architects are pretty crazy, but we knew we had to take a different approach,” said Clark. “We have been working on the frequency and the performance for decades, and we have really good tools for this. We have really good tools for power as well. But we had never really intersected power at the beginning of a grounds up core into the microarchitecture, really looking at every feature we are adding and being able to really understand the power it was going to draw running real workloads and evaluate a feature trade off that early in the design process. We were usually applying the power analysis much later in the design flow, really at a point where the key architectural decisions had been made and there was way less flexibility to go attack any power problems. They might be fundamental in the architecture.”
My estimate still stands. I expect the performance to be good but frequencies limited at launch. So from the above possibilities, I would say they've skewed to a 55/28/17 PPF split
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(Opinions are own)