In some ways x86 is much more inefficient:
agner in 2009 said:
agner in 2009 said:
agner in 2009 said:
agner in 2009 said:
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In some ways x86 is much more inefficient:x86 chips aren't intrinsically less efficient than ARM chips.
agner in 2009 said:The current x86 instruction set is the result of a long evolution which has involved many short-sighted decisions and patches.
agner in 2009 said:The problem with the overcrowded instruction code space has been dealt with from time to time by several workarounds and patches. Today, there are far more than a thousand different instruction codes, and many of them use complicated combinations of escape codes, prefix bytes, and postfix bytes to distinguish the different instructions. This makes instructions longer than necessary and, more importantly, it makes the decoding of the instructions complicated.
agner in 2009 said:PR considerations often have more weight than technical considerations. Currently, we have far more than a thousand instructions in the x86 instruction set. This is more than any programmer can memorize. It would be better to have fewer instructions and make each instruction more flexible so that it would cover more applications. But there is an obvious PR value in announcing that the newest processor has a bazillion new instructions. The weird and sometimes deliberately misleading names of the instruction set extensions are obviously decided by PR people rather than by technicians.
agner in 2009 said:Unfair competition. The market often favors Intel instructions rather than AMD or VIA instructions for compatibility reasons. The latter companies can only copy new Intel instructions with a delay of a few years. AMD does not have access to a fair share of the opcode space to use for their innovations. Historically, AMD has used small corners of the opcode space to avoid the risk that Intel might assign another instruction to the same code. There is no part of the huge VEX opcode space that AMD can safely use without permission from Intel.
Feedback from users is always too late. When a new instruction set is published, there is often public criticism, but then it is too late to change anything. The secrecy around innovations makes it impossible to involve the larger software community in the decision making process.
PR considerations often have more weight than technical considerations.
Sub-optimal solutions. Some instructions could be implemented better at no extra costs. For example, the PANDN and PALIGNR instructions would be more efficient if the two operands were swapped. A public discussion would have corrected such lapses before it was too late.
The competition in the microprocessor market has certainly been good for the price and performance of CPUs, but it has not been good for the compatibility. In May 2009, AMD published a revision of their plans where they modified the coding scheme for better compatibility with AVX. In addition to a full support of AVX, the revised AMD plan contains most of the original SSE5 instructions under the new name XOP and with the new coding scheme. Unfortunately, Intel had changed their plans in the meantime! In December 2008, Intel published a revision of their plans which involved a change of the coding of the fused multiply-and-add (FMA) instructions. Now it was too late for AMD to change their design once more, so the first AMD processors with FMA will follow the premature Intel specification rather than Intel's later revision. It is difficult to obtain compatibility when you are following a moving target.
Most programmers don't care what is going on at the machine code level, so they can't see all the ridiculous consequences that this war has.
Yes, that must be it !Moreover, why are you posting intel marketing slides in a thread about AMD Zen? Are you just here to thread crap and push an agenda, along with your absurd marketing slides?
Stick with us, champ. We were talking about future litho...Uh, what mobile phone chip contracts would those be? From what I've seen over the last 10 years
x86 chips aren't intrinsically less efficient than ARM chips. There's a nice ExtremeTech article that analyzed it.
x86 isn't that easy to emulate.
PowerPC is a relatively easy architecture to emulate. x86 and x64 are different beasts.
Finally, I've found the ExtremTech article.
Sure. That's what I expect.
Regarding Rosetta, it ran at about half the speed of a PowerPC. And, as I said, PowerPC is easier to emulate.
There's no doubt that current processors can run a JITer much better, but nevertheless x86/x64 is much more difficult to emulate, and I want to see how fluent is the emulation.
this has been exceedingly interesting the last couple pages but maybe you guys should break it into its own thread?
http://semiaccurate.com/forums/showpost.php?p=273707&postcount=3858So what month will we finally get to learn more about summit ridge? November?
unlocked multiplier: if the chipset supports it
Thats not what i wanted to read. Same crap with Intel, this will be a fail if we cannot OC with every chipset.
Why? It's good old fashioned segmentation at work. Want the additional features? Buy the better motherboards with better chipsets. This helps AMD's MB partners more than anything else, gives them incentive to design good enthusiast boards.
So what month will we finally get to learn more about summit ridge? November?
Thats not what i wanted to read. Same crap with Intel, this will be a fail if we cannot OC with every chipset.
Why? It's good old fashioned segmentation at work. Want the additional features? Buy the better motherboards with better chipsets. This helps AMD's MB partners more than anything else, gives them incentive to design good enthusiast boards.
+65% per-clock comparison with PD, if true it might be quite a leap compared to +40% against Excavator, because there might be <20% difference between PD and EXV.
The whole post is a joke (as in, it's actually a gag). There's no actual data. He's saying that the webinar had no information in a cute way. It's still 40% over Excavator based on internal estimates.+65% per-clock comparison with PD, if true it might be quite a leap compared to +40% against Excavator, because there might be <20% difference between PD and EXV.
...Based on a random unknown benchmark.It's still 40% over Excavator based on internal estimates.
A single, self written, znver1 optimized small loop fitting in the uop$ with a L1D$ friendly working set for those assuming an "up to" statement....Based on a random unknown benchmark.
Sent from HTC 10
(Opinions are own)
Thanks AMDA single, self written, znver1 optimized small loop fitting in the uop$ with a L1D$ friendly working set for those assuming an "up to" statement.
A single, self written, znver1 optimized small loop fitting in the uop$ with a L1D$ friendly working set for those assuming an "up to" statement.
The most interesting thing that pops out in this interview is this:
Papermaster: We’re committed to open source software. You look at our microprocessor, we have an LLVM open source compiler to optimize the performance you get out of the CPU. When you look at accelerators, GPUs, we took our stack and put in open source. If you go to www.gpuopen.com you’ll see the software and the tools it takes to accelerate using our Radeon technology.