New Zen microarchitecture details

[Abwx]

Transcript of Mark Papermaster interview at the Deutsche Bank 2016 Technology Conference :

https://www.reddit.com/r/Amd/comments/52urhi/advanced_micro_devices_amd_management_presents_at/

Some interesting technical infos from first hand...

 

[Dresdenboy]

The most interesting thing that pops out in this interview is this:


One does have to wonder, is the reason for the 40% increase in IPC because the internal tests they did are with a LLVM compiler that is optimized for Zen?

If that is the case, what would be the IPC increase for code that hasn't been optimized for Zen?

Depending on the delta between a new uarch and the one which is the base for generic or Intelish optimizations, this might be small (5%) or like for BD rather big (20+%).

 

[Hossain84]

Very interesting

 

[KTE]

Transcript of Mark Papermaster interview at the Deutsche Bank 2016 Technology Conference :

https://www.reddit.com/r/Amd/comments/52urhi/advanced_micro_devices_amd_management_presents_at/

Some interesting technical infos from first hand...

Wish washy language.

But looking at that, he seems very confident for an average 40% across the board, and good clocking/power.

Then why the large delay and lack of infos.

The two just do not add up for the corporate world.


Sent from HTC 10
(Opinions are own)

 

[USER8000]

Wish washy language.

But looking at that, he seems very confident for an average 40% across the board, and good clocking/power.

Then why the large delay and lack of infos.

The two just do not add up for the corporate world.


Sent from HTC 10
(Opinions are own)

Maybe,yields of parts hitting sufficient clockspeeds are the issue if AMD is using Globalfoundries??

 

[ShintaiDK]

Maybe,yields of parts hitting sufficient clockspeeds are the issue if AMD is using Globalfoundries??

Or its the issue of AMDs design?

 

[Abwx]

The two just do not add up for the corporate world.

To the contrary, because that was during the Deutsche Bank 2016 Technology Conference....

Corporate are interested by the potential of a technology, and they have boat loads of engineers to analyse what the interviewed representatives are talking about.

Other than this it s not only the CTO who seems optimistic, it s whoever AMD engineer is allowed to talk about the design, you surely noticed that marketing guys are totally absent from AMD com about zen...

 

[KTE]

Or its the issue of AMDs design?

What do you suspect? That it wont hit SNB/IVB performance?

Sent from HTC 10
(Opinions are own)

 

[Abwx]

Maybe,yields of parts hitting sufficient clockspeeds are the issue if AMD is using Globalfoundries??

If they can hit confidently 4.3GHz with 28nm wich is slower than 14nm LPP, why wouldnt they hit say 4GHz with this latter node..?.

At the end i wonder if you only half thought about this before posting, it s just too logical to have been missed..

 

[USER8000]

If they can hit confidently 4.3GHz with 28nm wich is slower than 14nm LPP, why wouldnt they hit say 4GHz with this latter node..?.

At the end i wonder if you only half thought about this before posting, it s just too logical to have been missed..

Because Globalfoundries has a history of having issues like this?? Remember when Kaveri came out,it was delayed and did not hit the TFLOPS targets which were originally hinted at by AMD and that was down to missed clockspeed targets??

32NM clocked better than 28NM and only now are we seeing generally better clockspeeds for production parts after a few years. 32NM was also problematic - Llano hit very low clockspeeds and Bulldozer released with not much higher stock clockspeeds than the Phenom II either despite the delays.

There is no guarantee Globalfoundries is not having issues with their first mass production Finfet chips hitting sufficiently high clockspeeds,so AMD needs more time for them to work on that metric.

Enthusiast desktop parts will no doubt be expected to run at higher clockspeeds than the server parts,so I expect the latter to be released first which increasingly looks like what is happening.

 

[ShintaiDK]

What do you suspect? That it wont hit SNB/IVB performance?

Sent from HTC 10
(Opinions are own)

In terms of clock and IPC? No. Personally I think SB or a tad below in IPC. Even with SB or IB IPC, clocks are so far behind it ruins it. And perf/watt doesn't look good at all.

Look at it this way, even 40% IPC increase over XV. But clocks down to ~3Ghz. The 65W Zen quad isn't going to be much more special than the A12 9800 APU that includes IGP at the same 65W.

 

[Abwx]

Remember when Kaveri came out,it was delayed and did not hit the TFLOPS targets which were originally hinted at by AMD and that was down to missed clockspeed targets??

But it was realeased at up to 3.9GHz with the first GF 28nm waffers, 14nm has more maturity in comparison for a CPU launch since they already released a product using ths node, what did they release before Kaveri using 28nm from GF..?...

And as already said 14nm is faster than 28nm, particularly the early 28nm you re using as "argument", actually you re ,unwillingly, proving the contrary of what you intended to...

 

[Glo.]

Maybe,yields of parts hitting sufficient clockspeeds are the issue if AMD is using Globalfoundries??

Or maybe they have partners, and they scheduled all of this to keep some things secret?

 

[KTE]

In terms of clock and IPC? No. Personally I think SB or a tad below in IPC. Even with SB or IB IPC, clocks are so far behind it ruins it. And perf/watt doesn't look good at all.

Look at it this way, even 40% IPC increase over XV. But clocks down to ~3Ghz. The 65W Zen quad isn't going to be much more special than the A12 9800 APU that includes IGP at the same 65W.

Personally, it's not the IPC I'm worried about... But the clock speeds and clock speeds@power.

Some of these highly paid analysts needs to ask him about clockspeeds. I can't believe no one has already.

Sent from HTC 10
(Opinions are own)

 

[AtenRa]

Personally, it's not the IPC I'm worried about... But the clock speeds and clock speeds@power.

Some of these highly paid analysts needs to ask him about clockspeeds. I can't believe no one has already.

Sent from HTC 10
(Opinions are own)

I dont believe anyone in AMD would answer questions like this before official NDAs lift.

 

[bjt2]

Because Globalfoundries has a history of having issues like this?? Remember when Kaveri came out,it was delayed and did not hit the TFLOPS targets which were originally hinted at by AMD and that was down to missed clockspeed targets??

32NM clocked better than 28NM and only now are we seeing generally better clockspeeds for production parts after a few years. 32NM was also problematic - Llano hit very low clockspeeds and Bulldozer released with not much higher stock clockspeeds than the Phenom II either despite the delays.

There is no guarantee Globalfoundries is not having issues with their first mass production Finfet chips hitting sufficiently high clockspeeds,so AMD needs more time for them to work on that metric.

Enthusiast desktop parts will no doubt be expected to run at higher clockspeeds than the server parts,so I expect the latter to be released first which increasingly looks like what is happening.

Early polaris samples already clock higher than older 28nm architecture (1266 max vs how? 1150? I am talking of reference designs)... Why this should not happen with Zen?

 

[Arachnotronic]

Early polaris samples already clock higher than older 28nm architecture (1266 max vs how? 1150? I am talking of reference designs)... Why this should not happen with Zen?

Completely different architectures. Polaris is a tweaked Tonga-architecture GPU. Zen is a much different CPU from the Construction cores.

It's like asking why the Apple A10 can't clock as high as a Kaby Lake-Y chip -- totally different architectures, totally different designs.

 

[bjt2]

In terms of clock and IPC? No. Personally I think SB or a tad below in IPC. Even with SB or IB IPC, clocks are so far behind it ruins it. And perf/watt doesn't look good at all.

Look at it this way, even 40% IPC increase over XV. But clocks down to ~3Ghz. The 65W Zen quad isn't going to be much more special than the A12 9800 APU that includes IGP at the same 65W.

Why do you think that a 4c 65W Zen, on 14nm FF, without IGP, should clock lower than 4c 65W XV, on 28nm BULK, with IGP?
Polaris already clocks higher than older 28nm architecture...

 

[bjt2]

Completely different architectures. Polaris is a tweaked Tonga-architecture GPU. Zen is a much different CPU from the Construction cores.

It's like asking why the Apple A10 can't clock as high as a Kaby Lake-Y chip -- totally different architectures, totally different designs.

Zen has a 19 stage integer pipeline.
Bulldozer is unknown, but between 15 and 20.
FO4 in the same ballpark.
So at same process they should clock similar.
But 14nm FF vs 28nm BULK on polaris gives +15% clock.

 

[Arachnotronic]

Zen has a 19 stage integer pipeline.
Bulldozer is unknown, but between 15 and 20.
FO4 in the same ballpark.
So at same process they should clock similar.
But 14nm FF vs 28nm BULK on polaris gives +15% clock.

I don't think it's as simple as you're making it out to be. But, we shall see.

 

[NostaSeronx]

Zen has a 19 stage integer pipeline.
Bulldozer is unknown, but between 15 and 20.
FO4 in the same ballpark.
So at same process they should clock similar.
But 14nm FF vs 28nm BULK on polaris gives +15% clock.

Yep.
Bulldozer is exactly 15 stages. On all designs from Bulldozer to Excavator.
FO4 is not the same.
Island series(7000 to 300) use single-bit flops, Star series(400 and onwards) use multi-bit flops.

 

[bjt2]

I don't think it's as simple as you're making it out to be. But, we shall see.

Are you saying that FO4 is a meaningless/unuseful metric?
I am talking of approximate frequency. I don't want to know with 100MHz precision.
These considerations tells us that at same transitors count, n Zen cores should clock at least as m BD cores, at same power.
Moreover official AMD statement is that (core to core I presume) the energy/cycle consumed is the same. So an 8c Zen should clock at 95W at the same clock of an hypotethical 8c XV at 95W... And so on...

 

[bjt2]

Yep.
Bulldozer is exactly 15 stages. On all designs from Bulldozer to Excavator.
FO4 is not the same.
Island series(7000 to 300) use single-bit flops, Star series(400 and onwards) use multi-bit flops.

So Zen FO4 is lower?

EDIT: for clarity, i supposed same FO4 because assumed worst case of 20 stages for BD...

 

[Arachnotronic]

Are you saying that FO4 is a meaningless/unuseful metric?
I am talking of approximate frequency. I don't want to know with 100MHz precision.
These considerations tells us that at same transitors count, n Zen cores should clock at least as m BD cores, at same power.
Moreover official AMD statement is that (core to core I presume) the energy/cycle consumed is the same. So an 8c Zen should clock at 95W at the same clock of an hypotethical 8c XV at 95W... And so on...

Just saying it isn't that simple. There's a reason AMD demo'd a 3ghz Zen against a 3ghz underclocked BDW-E.

It ain't because Zen can hit the crazy clocks that Piledriver could.

 

[Abwx]

Early polaris samples already clock higher than older 28nm architecture (1266 max vs how? 1150? I am talking of reference designs)... Why this should not happen with Zen?

At this point they know of course at wich frequency it will be clocked, and likely that it will be in the same ballpark as their current designs, for whom is interested in real info rather than fudistic theories, mainly brought by a given public out of fear that AMD could rival Intel in their strongholds, AMD explicitely stated that 14nm allow higher frequencies at much lower power, for relative frequency as well as for absolute one, in one word 14nm clock higher than 28nm at lower power..

This was released with the other Zen slides when they did their Blender demo, so the graph is related to their CPUs frequencies and efficencies, we dont even need a graduated vertical and horizontal scales, the curves are explicit enough..