New Zen microarchitecture details

[bjt2]

We'll see when it hits us, shall we ?

Yes. But let me do substantiated and backed up claims, to disprove other unsubstantiated claim...
If someone says X, with X not an opinion but a statement, i would prefer that he/she provides also proof or reasoning...

 

[AtenRa]

It is not same meaning.Something being inhomogeneous doesn't mean it's heterogeneous;as always context.
Edit: Ah,yes,most appropriate word in this case is variance.

Inhomogeneous is a synonym to Heterogeneous

 

[zinfamous]

I never thought of that term. The italian word was "disomogeneo", the opposite of "omogeneo" homogeneous.

In the scientific paper we used that term to describe the inhomogeneity of the magnetic field in a magnetic resonance machine (i am a medical imaging researcher)...

ah, that makes sense. You're talking about one type of field, or "thing," just variable in presence/strength/location? That would be different than heterogeneous: different types of "things"

I used to speak Italian, sorta, but that was a long time ago, and never in the science world.

 

[lolfail9001]

We can check the thing using the numbers rather than urban legends, the 4770K score 791, that is about 24% more than the FX8350, now let see two different renderers both optimised for HW FPUs :

What i see on your links is strong suggestion of FMA magic in action. So, yes, his point stands true: Cinebench differences are explained by lack of fancy instructions.

If someone says X, with X not an opinion but a statement, i would prefer that he/she provides also proof or reasoning...

My proof of reasoning is elementary: if Zen hits 94W at PSU rail on 3.3Ghz in a relatively light load, no chance in hell, it will have 95W TDP with 4Ghz clock on 8 cores. On 4 cores it is not unlikely, though words of AMD Polaris guy suggest otherwise. But on 8? As much of a chance as me killing my own dog.

 

[realibrad]

ah, that makes sense. You're talking about one type of field, or "thing," just variable in presence/strength/location? That would be different than heterogeneous: different types of "things"

I used to speak Italian, sorta, but that was a long time ago, and never in the science world.

Pizza pie!

nailed it.

 

[AtenRa]

What i see on your links is strong suggestion of FMA magic in action. So, yes, his point stands true: Cinebench differences are explained by lack of fancy instructions.

My proof of reasoning is elementary: if Zen hits 94W at PSU rail on 3.3Ghz in a relatively light load, no chance in hell, it will have 95W TDP with 4Ghz clock on 8 cores. On 4 cores it is not unlikely, though words of AMD Polaris guy suggest otherwise. But on 8? As much of a chance as me killing my own dog.

TDP is not power usage,

Take a look at FX 6350 that with 3Modules and 6Threads at the same 125W TDP has lower base Clocks than 4Module 8Threads FX8350

Im not saying 8C ZEN will have 4GHz base but taking TDP as power usage is wrong.

 

[zinfamous]

Pizza pie!

nailed it.

kinda, but it was more like this:

https://www.youtube.com/watch?v=kQA07B0X6jU

I was able to keep myself fed with pancetta, wild boar sandwiches, and chianti for about 5 months, so I considered myself fluent enough.

 

[bjt2]

What i see on your links is strong suggestion of FMA magic in action. So, yes, his point stands true: Cinebench differences are explained by lack of fancy instructions.

My proof of reasoning is elementary: if Zen hits 94W at PSU rail on 3.3Ghz in a relatively light load, no chance in hell, it will have 95W TDP with 4Ghz clock on 8 cores. On 4 cores it is not unlikely, though words of AMD Polaris guy suggest otherwise. But on 8? As much of a chance as me killing my own dog.

4GHz maybe i was too optimistic, but keep in mind that the clock was 3.4GHz, the sample was slightly overvolted and we don't know what step it was. I woudl expect at least 3.6GHz base and an all core turbo near 4GHz.
If i understand well XFR, we may not have anymore these fixed clock, but we have a minimum (base), a maximum guaranteed in single thread and light load and then headroom depending of the heatsink and the load. I would expect mean clocks depending on the application, regardless of threads spawned. E.g. maybe with a 16 thread light load can clock at X and a 12 thread stronger load can clock lower...

 

[lolfail9001]

the sample was slightly overvolted

Allegedly.

we don't know what step it was.

A0c or A0d, obviously.

If i understand well XFR, we may not have anymore these fixed clock, but we have a minimum (base), a maximum guaranteed in single thread and light load and then headroom depending of the heatsink and the load.

You get it mostly right, basically nV's GPU boost, but for CPU. Benchmarking is going to be not fun.

 

[.vodka]

You get it mostly right, basically nV's GPU boost, but for CPU. Benchmarking is going to be not fun.

Not really. This CPU will ship with the wraith cooler, which is at the level of an Hyper 212 evo more or less. That should be enough for cooling this thing and allow good performance. They should definitely inform ambient temperature at the time of testing, and temps/clocks throughout the tests. That data is going to be fun to analyze.

Besides, from what I've read the XFR setting can be disabled, so that should make things easier.

 

[The Stilt]

A0c or A0d, obviously.

"New Horizon" demos ran on a system with B1 stepping CPU in it.

 

[raghu78]

"New Horizon" demos ran on a system with B1 stepping CPU in it.

Whats the source for that information ? AMD obviously gave no such information.

 

[The Stilt]

Whats the source for that information ? AMD obviously gave no such information.

Fine, I just made that up.

 

[inf64]

"New Horizon" demos ran on a system with B1 stepping CPU in it.

Do you think that this will be the stepping they will launch ?

 

[itsmydamnation]

It's extremely unlikely Zen can hit 4+GHz and even come close to being kept cool by products expecting a 95w TDP. It was said they upped the voltage a bit for their 3.4GHz demo, not something needed for a chip that is comfortably hitting 4GHz near stock voltage.

If Zen had that kind of performance efficiency, compared to their 3.4GHz demo, the consumer release would be pushed back to 3Q/4Q so AMD could supply 100s of thousands of chips a quarter to Facebook, Google, Amazon etc.

NO,

server validation takes significantly longer the consumer validation. They will release to server guys the second they can.

Guys give the stilt a break, just because he was wrong on some stuff doesn't mean he doesn't have lots of worth while knowledge and information.

The problem with all those IPC guesstimates is no one actually looked at the design (i hate to be that guy, but i told you so lol) just ran with a single number. Apple can get +20% IPC over skylake but amd only -20% with cache latency/core width/pipeline length all approx equal. People will then throw around R&D spend as a justification for that position while completely ignoring the evolutionary aspect of Core design, there is only one or two "NEW" things in Zen. Hell even the FPU is a design following on from a white paper that came out before Bulldozer...

 

[The Stilt]

Do you think that this will be the stepping they will launch ?

Your guess is as good as mine, however consider the factor time plays in this. For the ability to ship in volume in March, mass production must be running now.

 

[KTE]

^*^sven: yes, but early rev, early board platform power doesn't mean much on a light load (60% on my Broadwell). Even if they coiled the rails to measure current, or used a shunt. Very little is known how Zen even draws power (rails/pins)...

Nehalem for instance drew through ATX 24-pin 3.3/5v as well as CPU 12v.

Sent from HTC 10
(Opinions are own)

 

[Doom2pro]

Your guess is as good as mine, however consider the factor time plays in this. For the ability to ship in volume in March, mass production must be running now.

They have TWO months to get volume availability, Global Foundries has 60k wafers a month, add Samsung's two Fabs to the mix (Korea and Austin TX), then add packaging & testing overhead.

I doubt they need to be mass producing RIGHT NOW, they still have a little more time.

 

[leoneazzurro]

From tapeout to finished product it takes 3 months at least, so the final stepping must be in production now. A wafer does not take zero time to produce, quite the opposite.

 

[superstition]

Lower FO4.

I guess they're improved things a lot since these posts:

The Fmax vs. Vdd curve on 14nm LPP is vastly steeper than on 28nm HPP, close and beyond the optimal Fmax range. 14nm LPP is superior to 28nm HPP when it operates at it's optimal range, but anything outside this range is far inferior.

I don't expect 14nm LPP to gain any additional frequency capabilities due maturation, but I expect it to become much more consistent and efficient due to it.

The biggest obstacle for Zeppelin reaching high Fmax is IMO: The manufacturing process itself & the aggressive L2 latency.

If someone asked me to estimate the Fmax of Piledriver which would have the same L2 latency (and reduced size) as Zeppelin does, my estimation would be around 3.6GHz. And that's on the 32nm SHP SOI process, at its peak.

Below 4.2GHz the 32nm SOI (Super High Performance) process is working at its most efficient range. Above 2.5GHz 14nm LPP (Low Power) is already expected to operate well beyond it's most efficient range.

I guess the delay was worthwhile.

 

[superstition]

Ask the_stilt. Hé Will explain you how zen on 14lpp is limited to 2.8/3.2ghz turbo.
Best process analyst ever.

I read a rumor article a while back that said AMD improved the performance of the node by 50% or something and it was going to be used for a new iteration of Polaris with better efficiency in Q1. I don't recall the specific details but these Zen clocks look like the massive improvement to the process happened.

Does GoFlo have a secretive 14nm medium power or high power process no one knew about?

 

[mikk]

It s the other way around, Cinebench R15 give Intel s CPUs an advantage that they could actually get only thanks to said new instructions.

Wrong. Cinebench doesn't use AVX or FMA instructions.

 

[iBoMbY]

I read a rumor article a while back that said AMD improved the performance of the node by 50% or something and it was going to be used for a new iteration of Polaris with better efficiency in Q1. I don't recall the specific details but these Zen clocks look like the massive improvement to the process happened.

Does GoFlo have a secretive 14nm medium power or high power process no one knew about?

It is possible Polaris started on 14LPE, and was (or will be) moved to 14LPP.

 

[krumme]

It is possible Polaris started on 14LPE, and was (or will be) moved to 14LPP.

Perjaps...Or perhaps polaris was just a temporary console biproduct on 14lpe funded by Sony only used untill vega will come on 14lpp. Perhaps vega will later come in more than the two big sizes that we asume?

 

[Doom2pro]

I read a rumor article a while back that said AMD improved the performance of the node by 50% or something and it was going to be used for a new iteration of Polaris with better efficiency in Q1. I don't recall the specific details but these Zen clocks look like the massive improvement to the process happened.

Does GoFlo have a secretive 14nm medium power or high power process no one knew about?

14LPP doesn't require low power and isn't limited to low clocks, as others have said, you can hit the efficiency sweet spot designed for 14LPP or go outside that range to get higher clocks at the cost of higher power.

Polaris, Zen & Vega are 14LPP... If you want, you can say Polaris was a 14LPP "pipe cleaner" for Zen & Vega... The node knowledge gained from running Polaris (and other products) through 14LPP will benefit Zen & Vega and the only question is, does this node knowledge flow between Global Foundries and Samsung, and if so, is it bidirectional?