IPC of a single thread fluctuates a lot. So it's good to be able to share those ALUs between two threads depending on the individual thread's needs.Not for the Integer,
BD Module has 4x Integer ALUs + 4x AGUs
ZEN Core has 4x Integer ALUs + 2x AGUs.
Not for the Integer,
BD Module has 4x Integer ALUs + 4x AGUs
ZEN Core has 4x Integer ALUs + 2x AGUs.
Yes.
Rude!
But seriously, Nosta, 2/3 of the stuff you say never materializes. Are those Harvester and Crane dice still in the works, or...?
NostaSeronx's posts are generally not grounded in reality and should not be relied upon for any serious analysis/decision making. Entertainment purposes only, but at this point it's not even funny, it's just sad.
The GF14HP node was apparently not marketed as much as 22FDX.Nosta, 2/3 of the stuff you say never materializes.
14HP Design Rule Development Intern,
-Summer Intern-14HP Design Rule Development at GLOBALFOUNDRIES, U.S
-Support of 14nm High Performance Design Rule Development
IBM assignee at GlobalFoundries, working on 14HP BEOL integration
working on 14HP BEOL integration to support 14nm chip production for IBM Server Group
14HP Lead Manufacturing Integrator, Responsible for coordinating manufacturing and volume production readiness activities for 14nm SOI technologies.
CMOS Device Modeling Engineer,
Delivered FEOL, MOL and BEOL passive device compact models in world-class PDK for multiple generations of SOI and bulk CMOS technology nodes: 32SOI, 20LPE, 22SOI, 14SOI/14HP, 10nm and 7nm.
One of the big things to note is that ALL three 300mm foundries from GlobalFoundries will be doing GF22FDX and GF14HP. Some profiles doing 22FDX EDA-related work are now recently doing 14HP work. The ditch of FX14/14LPP basically means only Samsung foundries will be doing Samsung nodes.Fellow, Advanced Technology Development, Advanced Technology Development - Integration and Device Design Group at GLOBALFOUNDRIES.
Responsible for 14HP, 10nm and 7nm Technology Development
Maybe. 14XM Bulldozer added a lot of things to 15h.Are those Harvester and Crane dice still in the works, or...?
I seems GF14HP is an internal name for Samsungs 14LPP
Where is the proof of this? D:1. These "misdeeds" intentionally caused unrecoverable damage to x86.
Where is the proof of this? D:
Indeed, very interesting. We're fixated on TSMC, GF/Samsung and forgotten about IBM. Hmm.
Where is the proof of this? D:
What? http://www.cnet.com/news/intel-to-pay-amd-1-25-billion-in-antitrust-settlement/
AMD produced better silicon during the Pentium 4 days so Intel used its massive amounts of cash to pay off OEM's to continue to use their inferior hardware.
Please disregard if you were joking.
What do you need proof of? The "misdeeds" are common knowledge. Heck, they've been found guilty of anticompetition in almost every western nation (and a few easterns).
As for the irreparable damage, how many x86 manufacturers do you see nowadays?
14HP is most likely IBM's 14nm high performance node to be used to build POWER9. In fact, it's literally right there in Nosta's quotes.
The GF14HP node was apparently not marketed as much as 22FDX.
Blips of GlobalFoundries' 14nm HP FinFET that is no way related to Samsung's 14LPE/14LPP from linkedin;One of the big things to note is that ALL three 300mm foundries from GlobalFoundries will be doing GF22FDX and GF14HP. Some profiles doing 22FDX EDA-related work are now recently doing 14HP work. The ditch of FX14/14LPP basically means only Samsung foundries will be doing Samsung nodes.Maybe. 14XM Bulldozer added a lot of things to 15h.
Floating Point; FP128+FP256 (FN8000_001A_EAX // FP256_V=1 // FP128_V=1), 2 FP256 to 4 FP128, the units are more uniform implying MMX being fused into FMAC units. Which was seen with Steamroller/Excavator w/ P0 and P2 being fused from Bulldozer/Piledriver.
Gen. Execution; AGUs have adders for ADD, SUB, Convert, Shift, etc. // ALUs are uniform; 2 imuls, 2 idivs, 2 branch, 2 jumps
Front-end and cache; L2 is Jag/Leo/Mar derivived replacing the larger, more slow L2 design. That has been seen in every 15h design to date. Much faster usage latency, same read/write latency as Steamroller/Excavator though. L1D is implied to have three ports; Read/Write for port 0, Write for port 1, Load for port 2. 1RW1W1R(4 reads + 4 writes) instead of 2R1W(4 reads + 2 writes). Branch predictor and L1i+Fetch split for more single threaded performance. Saw the less complete split with Steamroller/Excavator.
Misc; AVFS which was added to Excavator, AFS which was added to Steamroller, and IVR which hasn't popped up yet.
14HP is most likely IBM's 14nm high performance node to be used to build POWER9. In fact, it's literally right there in Nosta's quotes.
People keep wanting to blame Intel for AMD's incompetence
I'd love to upgrade to a good AMD chip. I hope they get good again.
Can you quote some of those "people" please. All I have seen Intel blamed for was illegal business practices.
1. These "misdeeds" intentionally caused unrecoverable damage to x86.
2. These "misdeeds" historically happen when a company releases something competitive with intel (386, athlon)
3. These "misdeeds" make the arguement of a competitive product moot.
I'm asking about the irreparable harm.
Wow, what a weak proof for your argument.
Back during the time just before Intel was playing funny games, how many x86 manufacturers were there?
Same as today, Intel, AMD, VIA.
People keep wanting to blame Intel for AMD's incompetence, yet forget that AMD were capacity constrained during their x64 days, so they sold every processor they could make, yet some continue with the fantasy that they could have sold so much more.