If you know how to use statistics to get a better view of the world, you have to accept, that one sample is not enough to get a good overall impression. CB (any version) is nothing more than a rough indication with two digit error margins.The update decreased Intels advantage slightly, but it was very minor. No issue since Cinebench is a nice benchmark that reflects real world. There is no favour for either Intel or AMD, it's a good
average value. You can be sure if AMD releases a competitive µarch in the future it will show up in Cinebench.
Is "F3" = B1?Bx stepping became available extremely recently, in early December. That's most likely the reason why they allegedly overvolted it during the demo (i.e untested / validated silicon).
Is "F3" = B1?
1D3201A2M88F3_35/32_N
BTW, iBoMbY found something interesting (and actually in plain sight all the time):
1D3201A2M88F3_35/32_N - 3.20GHz base
2D3151A2M88E4_35/31_N - 3.15GHz base
So the "multiprocessing" code (according to CPU World) is just one letter/number: "1".
We thought so, but I've seen ES OPNs w/ and w/o SMT having a "1". It's just CPU-World saying so:"Multiprocessing code" refers to SMT or something else?
LP curve will ALWAYS be lower in Clocks/Power than a HP curve. That's exactly why they are created and thus aptly named 'Low Power Plus'. IBM isn't naive to develop SHP for its highest performance, highest clocking chips14LPP doesn't require low power and isn't limited to low clocks, as others have said, you can hit the efficiency sweet spot designed for 14LPP or go outside that range to get higher clocks at the cost of higher power.
It looks to me like a logical replacement to the 4-pin peripheral connector that motherboard manufacturers have been using for years to add an additional 12V pin for hungry PCIe cards. It makes a lot of sense really and I've wondered before why they haven't used it in the past. Not only do you move from one 12V pin to three, but that motherboard 4 pin is probably the only old school 4 pin thing left in their case. Might as well get rid of it.There are some pictures of new MSI AM4 boards: http://ocaholic.ch/modules/news/article.php?storyid=15959
The X370 board looks like 8+2 VRM, and has a 8-pin and 4-pin EPS connector. Seems like it is designed for a little bit more than 95W TDP ...
Edit: There also is a 6-Pin PCIe socket at the bottom of the board, which is probably why there is an additional 4-Pin socket. Could this be something about PCIe 4.0 requirements?
The Stilt :
40% IPC more than Excavator base on what ? There is no standard definition for IPC.one Is slower than BD, one Is faster BD.It's that representation of IPC ?
Is "F3" = B1?
1D3201A2M88F3_35/32_N
BTW, iBoMbY found something interesting (and actually in plain sight all the time):
1D3201A2M88F3_35/32_N - 3.20GHz base
2D3151A2M88E4_35/31_N - 3.15GHz base
So the "multiprocessing" code (according to CPU World) is just one letter/number: "1".
Sorry, I wasn't clear enough. I meant the 6th place in the string. But this is nice to know, of course.B0 or B1, but I cannot be sure which.
The first character (1/2) should be simply part status (1 = Validated ES, 2 = Prototype ES), meaning identical parts can be either 1/2 depending on the time they are produced (pre / post validation).
LP curve will ALWAYS be lower in Clocks/Power than a HP curve. That's exactly why they are created and thus aptly named 'Low Power Plus'. IBM isn't naive to develop SHP for its highest performance, highest clocking chips
Traditionally, LP has 100-1000x lower leakage at the same voltage/temp, lower on the frequency curve.
Intels 45nm HKMG brought 1000x lower leakage than 65nm!
That NEVER means 100-1000x lower CPU power
Example with Intels 22nm transistor curves:
LP process is typical for mobile parts, or used if a HP is not yet available, or if it offers the required power without sacrificing too much on the clocks. But there's always a hit in clocks from an equivalent MFGs HP process, even if the HP is subnormal.
RE TheStilt: he gave some predictions, and it seems he's been more right than most here.
But I did say there is no way A0 will launch. B1 was what I and some others thought will be launch step, if there were no major bugs. If the rumored uop/SMT bug is chip level, then I'd expect B2 to be launch stepping.
Sent from HTC 10
(Opinions are own)
The update decreased Intels advantage slightly, but it was very minor.
It looks to me like a logical replacement to the 4-pin peripheral connector that motherboard manufacturers have been using for years to add an additional 12V pin for hungry PCIe cards. It makes a lot of sense really and I've wondered before why they haven't used it in the past. Not only do you move from one 12V pin to three, but that motherboard 4 pin is probably the only old school 4 pin thing left in their case. Might as well get rid of it.
Sorry, I wasn't clear enough. I meant the 6th place in the string. But this is nice to know, of course.
That still means nothing in response to what I said?For 14nm LPP there are 3 ranges of transistors, as i posted: HVT, RVT and LVT transistors... The difference between them is leakage and threshold.
Actually, I just did a double take there. That 6 pin on the bottom isn't a PCIe power connector. It's a 6 pin Minifit-Jr with a standard keying. Very strange.
That still means nothing in response to what I said?
What's the transistor leakage and drive currents for 14nm LPP?
That is what decides slow or fast.
Those cell libraries exist for every other process too!
Low/High/Standard Vt logic cells have been used in combination since at least a decade. LVT in critical path/HVT in non-critical. LVT is faster but higher power. HVT have a lower power but bigger delay.
If that MSI X370 XPower Titanium doesn't feature Niko-Semi fets in the CPU VRM, it should be a quite decent board with it's 6+4 phase config. Most likely a 6+2 phase native, with the secondary plane doubled.
What is the point of doubling the secondary plane? I cant see this board being paired with top of the line APUs and their iGPs being overclocked to warrant extra phases to that particular power plane.
I apologize if this has been answered already but do we know how many PCI-E lanes AM4 is supposed to have?
The additional PCIe power connector seems to be a thing in the current MSI Titanium line of products.
http://wccftech.com/msi-am4-x370-motherboard-ryzen-cpu/
Seems to be for PCIe as some suggested:
"CPU is supplied through the 8+4 pin connector, the 24-pin ATX connector powers the board while an extra 6-pin power connector lies at the bottom to provide extra juice to the PCIe slots when running multiple GPUs."
I apologize if this has been answered already but do we know how many PCI-E lanes AM4 is supposed to have?