That's what he said, knowingly or otherwise :>So what your trying to say is Intel inherently have horrible over subscription on PCI when the CPU needs to access PCI devices?
So what your trying to say is Intel inherently have horrible over subscription on PCI when the CPU needs to access PCI devices?
Who do you think made the decision to have an F4 stepping as opposed to calling it a day at F3? Jim Keller who left months ago or the remaining Zen design leads + exec board?
Atari2600 said:Who do you think made the decision to have an F4 stepping as opposed to calling it a day at F3? Jim Keller who left months ago or the remaining Zen design leads + exec board?
That would be the CTO - Mark Papermaster. You know, the guy who is in charge of technology.
Good man, <<now>> your acknowledging that at least one executive board member will indeed be part of the decision to respin from F3 to F4.
Normally, I'd agree with you that it would stop there (at the CTO) - certainly in Intel that'd be the case.
But with so much riding on Zen, I'd say that was a decision that involved a few of the executive board (those with technical backgrounds and probably the marketeers for assessing impact). Lisa Su being one of them.
If you think there is 32, then document it.
You do realize the product hasn't been officially released yet?
And you recon I pulled the figure of 32 lanes out of my ass, or?
Most of the rumors say that there are 128 PCI-E Gen. 3 links on the SP3 server platform (Naples). This is accurate, and since each SP3 CPU consists of four separate Zeppelin dies in MCM config you can easily figure out what the per die number of links is.
And no, I'm not saying that AM4 platform will have all of these links available for use. Naples doesn't require a chipset, since there are obviously four internal FCHs (Taishan) in total already. Because of that it doesn't need to spend any of the actual PCI-E links for the chipset like AM4 does.
As far as I know it still looks exactly like this old picture:
This attitude is why boardrooms are so often completely ineffectual! Folks seemingly don't understand what they should or should not be doing!
This may help. I did these up based on Intel's style of Lane allocation diagrams( which are great IMO) in an attempt to ease comparisons. the z270 at the bottom is essentially a copy of that provided by Intel with CPU lanes added.
I queried the x8 CPU-FCH link, to see if I needed to redo it. But if we're assuming it's x4...
This is an interpretation of the information provided, some may be incorrect in reality. Throw corrections at me.
concentrating on X370 vs Z270 , I guess It shows the off the shelf flexibilty of intel's platform, but at the same time the lack of Direct connected functionality
Not all corporations are the same. Some top management as some companies like to get into the nitty gritty. Steve Jobs is a good example. He made a lot of technical decisions, including overriding engineering staff to do things like have the case for the Apple III designed before the innards (which led to the overheating issue since he also mandated no fan for aesthetics). He had a huge hand in the design elements of the NeXT Cube, like getting rid of a floppy in favor of a rewritable optical drive. Not all of Jobs' interventions were failures like that, though. Sometimes engineers don't make the best decisions. It goes both ways. Jobs didn't just ask engineers to show him nice stuff. If he had managed like that he would have been no different than the Gil Amelios and others at Apple who accomplished little. Jobs is the guy who was so impatient with tech that he'd demo prototypes instead of the machines with lesser specs that were actually going to be sold.With all due respect, some of the stuff about corporations/enterprise you're claiming make it pretty clear you have absolutely no idea about them in the real world and certainly have never worked with them.
Liking an execs role in the top IT companies to a far lower-level team manager/product architect is just the worst giveaway you could have made.
I realize what you 'think' or expect could be very different to the reality, but reality doesn't mould into shapes that we wish for, unfortunately.
I have a nvme hdd thats bitlockered and i am transferring data to it via USB3 ( or vis versa), what happens? I do this daily on a daily basisIts the standard since you dont use them all at the same time usually. You can look on the configurations on AM4 boards and then wonder how it would work without adding sharing somewhere, with PLX chips and regular limits. Its been the standard for AMD and Intel for ages and still is in the future.
What he has listed if factually correct, they are clearly labed SATAe.You picture gives an idea that the A320/B350/X370 chipset also offers useable PCIe 3.0 and that's incorrect..
And we all know that Bill Gates, particularly in the early going, was hardly someone who just massaged numbers and made business deals. He may not have been a genius programmer but he certainly understood what was going on on a technical level. He's the guy whose Extended BASIC became the hobbyist's higher standard, right? That's hardly someone who doesn't know technical details.
Yes, I am prone to using understatement to reinforce a point.That is actually understatement. Bill Gates actually had very good idea of what is going on.
I have to know WTF you're needing that for.The SFF I/O options are really a disappointment. Just 4 USB 3.0, no USB 3.1? Just 2x SATA600 + 1xNVMe x2 ? I need at least 6x USB, 3x SATA600 and would prefer a NVMe PCIe 3.0 x4...here's hoping someone will put an A320 into a mini-ITX board.
Maybe calling it 'really a disappointment' is comming off a bit to strong, I think it is neat to include everything that is needed for a notebook or NUC like device.The SFF I/O options are really a disappointment. Just 4 USB 3.0, no USB 3.1? Just 2x SATA600 + 1xNVMe x2 ? I need at least 6x USB, 3x SATA600 and would prefer a NVMe PCIe 3.0 x4...here's hoping someone will put an A320 into a mini-ITX board.