Isn't Steamroller a better overclocker than Excavator, mainly because it's using a performance library rather than a density library? I believe Anandtech covered this in an article at one point. What I wonder about both, though, is why their DRAM latency is so high, according to The Stilt, in comparison with PD.Actually 3.6/4.0 and with 45W less of TDP, and it's still an ES (so subject to improvements)...
The answer to your question is FO4.
AMD with Excavator reached 4.3GHz turbo on the 28nm BULK. With 4.9GHz of OC.
Only with Kabylake on the 14nm INTEL have bested it. Obviously the 28nm BULK is not magical. It's Excavator (and probabily also Zen) that has low FO4...
That was the chip I was thinking of. I just didn't remember that it actually beat Intel's stuff in memory performance. How long did that lead last?Regardless, the FX-51 results are unsurprising.
The Anandtech article is from well before BR.SR was only a better overclocker compared to Carrizo. Bristol Ridge has hit 4.8/4.9 GHz in some test runs on boards that you can't really buy, at least not in North America anyway (Asus' "Octopus" for example). Kaveri/Godavari is consistently only good for 4.7 GHz, with rare exceptions.
Until nehalem but they rolled with large L2 caches on C2D's that helped alot.That was the chip I was thinking of. I just didn't remember that it actually beat Intel's stuff in memory performance. How long did that lead last?
The Anandtech article is from well before BR.
Until nehalem but they rolled with large L2 caches on C2D's that helped alot.
Throughput of DIV and SQRT are worse on AMD than on Kaby Lake, especially on SSE, as you can see in the picture linked in Dresdenboy post.If you think of blender, for instance, a ray tracing algorithm for sure requires also divisions and SQRTs... In this case AMD will shine...
Plus the lack of OoO loads which was the Achilles Heel for the K8, and whatever latency improvements the IMC brought over C2D it was more than compensated by the C2D prefetchers.
Ok, i checked on INTEL manual and it seems that each pipe can do mul, add and fmac, 256 bit. But they are 2 pipes. On 128 bit/legacy code AMD has advantages.Who said that i was talking of VecInt set apart you..?..
One FPMUL in port 0 and one (FPMUL or a FPADD) in the port 1.
At the bottom of the page :
http://www.hardware.fr/news/29-08-2016/
It boost at 3.5 with all cores in about any condition, including Prime 95 if the FFT is not too small :
http://www.hardware.fr/articles/946-4/overclocking-consommation.html
Interestingly Canard PC measured SR's VFMADD132PD throughput to be 2x BR's throughput, or the same as KL (2/cycle).
SQRTPD gets executed on just 1 unit, DIVPD, too, while VDIVPD has a bit better throughput.
Edit:
I just found out about two new articles by Hiroshige Goto (auto translated to Googlish):
The integer unit of AMD's next generation CPU "ZEN" is completely different from the Bulldozer series
Floating point / SIMD unit of AMD next generation CPU "ZEN" of relatively mature design
Throughput of DIV and SQRT are worse on AMD than on Kaby Lake, especially on SSE, as you can see in the picture linked in Dresdenboy post.
Interestingly Canard PC measured SR's VFMADD132PD throughput to be 2x BR's throughput, or the same as KL (2/cycle).
SQRTPD gets executed on just 1 unit, DIVPD, too, while VDIVPD has a bit better throughput.
128bit or 256bit ?
128-bit, same instruction as CPC listed.
Sad, cause they listed 256bit VDIVPD thoughput for Skylake, a bit worthless comparison.
EDIT: kinda strange when industry veterans like Canard PC, make such mistakes in instruction table. Both FMA and VDIVPD somehow list 128 bit OPs for AMD and 256 bit OPs lat/TP for Intel. A strange way to paint more rosy picture than it is.
How many avx ops does there have to be in an instruction mix to fire up the 256bit paths for Haswell? Depending on the tests and workload those values could be valid.
VFMADD132PD is prolly operating on two doubles instead of four, so thoughput is 2.
Intels divisors are stuff of the legend, i think by Broadwell they had 10bit wide divisors, so their thoughput is like 2-3x fo what AMD has. Again, VDIVPD results from Canard make zero sense for Zen, probably two doubles instead of four are processed here. ( or DIVPD thoughput reported too low ).
They are correctly listed as 8 cycle TP, 256bit, if they were 128bit, their thoughput would be 4 cycles, so your theory does not apply. If 256bit path was not active, thoughput would be even less. It's Zen results that don't make sense for 256bit versus 128bit, clearly both ops are best case 128bit.
AFAIK INTEL arch have 256 bit units only on FADD, FMUL and FMAC. Other FP ops are limited at 128 bits...
If you look at Summit ridge it has twice the throughput of Bristol Ridge which doesn't make sense because they both have two FMA "units". So i went back and looked/listened to the hotchips presentation and nowhere does it list or say the pipes are 128bit or 256bit only that it has 128bit stores. So i have had a quick look and i cant find anywhere AMD says the SIMD pipes are 128bit.
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They say in their slides. "2 Floating point units x 128 FMACs." Unless "128" in their parlance means 256bits, they have 128bit FMACs
Sad, cause they listed 256bit VDIVPD thoughput for Skylake, a bit worthless comparison.
EDIT: kinda strange when industry veterans like Canard PC, make such mistakes in instruction table. Both FMA and VDIVPD somehow list 128 bit OPs for AMD and 256 bit OPs lat/TP for Intel. A strange way to paint more rosy picture than it is.
If you look at VFMADD132PD for bristol ridge it matches anger for latency and reciprocal throughput. Its also listed as 2 uops so its a 256bit op. If you look at Summit ridge it has twice the throughput of Bristol Ridge which doesn't make sense because they both have two FMA "units". So i went back and looked/listened to the hotchips presentation and nowhere does it list or say the pipes are 128bit or 256bit only that it has 128bit stores. So i have had a quick look and i cant find anywhere AMD says the SIMD pipes are 128bit.
I dont think its likely that CPC did the Bristol ridge and kaby lake tests right but Summit Ridge wrong. Maybe they do have 256bit units but are store limited so unless your tests keep lots of data in registers you only see the throughput improvement on long latency/ low throughput instructions?
edit: it would also make sense from a "SenseMI" perspective, i have wondered about some of the comments AMD reps have made around it. They would only make sense if you clock/power gated resources.