If the red rectangle is 15mm2 then the die is smaller than 200mm2
It would be nearly 200mm2 exactly.
If the red rectangle is 15mm2 then the die is smaller than 200mm2
That was in relation to XV/BR as we also discussed 28nm.Bulldozer die is 315mm2, 25% smaller is 236mm2. Do you believe the 8C ZEN die will be that large ??
Closer. There is one more hint.If the red rectangle is 15mm2 then the die is smaller than 200mm2
That was in relation to XV/BR as we also discussed 28nm.
Closer. There is one more hint.
To be fair to BWE, it has four memory channels compared to Ryzen's two.Thats pretty good.
BWE is supposed to be around 245 mm2.
I see where you're coming from, but BWE also has far more PCI-E links coming from the CPU than Ryzen does, so even though Ryzen has some SATA and USB controllers on there, I don't think the SoC aspect of Ryzen costs it anymore transistors than the extra PCI-E lanes from the CPU.Ryzen is a SoC. BRW-E not.
Ddr phy area ? Extrapolate from skl and xv?That was in relation to XV/BR as we also discussed 28nm.
Closer. There is one more hint.
For the lazy people:Right in the middle of my answer to Shintai.
At ~57% the 8C PD's die size, the cost disadvantage per wafer will be alleviated a bit.
How do you figure?In that case the yields, if the cost figures of 18/21$ per piece are right, are between 50% and 60%, possibly they will increase as time passes. In this case the margin if improvement is larger.
That's it. Of course this is just an estimation.For the lazy people:
Piledriver 8C is 314mm^2.
57% of that is 179mm^2.
Fairly certain a 14nm wafer doesn't cost 4k for AMD. It's probably the price for the foundry to manufacture it, without the cut to make a profit.If a wafer costs around 4K$ and a die costs between 18$-20$, then there should be around 200-220 good dies per wafer. A wafer area is a note number, with around 90% of that area available for dies. If you know the die size, then you can do the math. Given the uncertainty in wafer cost, die cost and die size only a rough number can be estimated. Not that this is the actual truth, it's only a guess based on the number given in this thread.
Fairly certain a 14nm wafer doesn't cost 4k for AMD. It's probably the price for the foundry to manufacture it, without the cut to make a profit.
It's probably more like 5k.
If the L3 cache is 15mm2 and it fits 12x in the die with a little room to spare, it must be above 180mm2?
:AREA WITH CCX @ 15mm^2:
mm/pixels: 0.0517mm
L3 Height: 4.602mm
L3 Width: 3.259mm
Die Height: 9.409mm
Die Width: 20.628
Die Area: 194.09mm^2
:CCX WITH AREA FROM 179mm^2:
Die Height: 9.036mm
Die Width: 19.808mm
mm/pixels: 0.0496mm
L3 Height: 4.418mm
L3 Width: 3.124mm
L3 Area: 13.801mm^2
An error of a few pixels might quickly add up by repeating it. I'd say, there is at least a 5% error in measurement. It was actually just done in a discussion related to adding L3.If the L3 cache is 15mm2 and it fits 12x in the die with a little room to spare, it must be above 180mm2?
Zen also has to pay a cost for the big inter soc interconnect.I see where you're coming from, but BWE also has far more PCI-E links coming from the CPU than Ryzen does, so even though Ryzen has some SATA and USB controllers on there, I don't think the SoC aspect of Ryzen costs it anymore transistors than the extra PCI-E lanes from the CPU.
An error of a few pixels might quickly add up by repeating it. I'd say, there is at least a 5% error in measurement. It was actually just done in a discussion related to adding L3.