lolfail9001
Golden Member
- Sep 9, 2016
- 1,056
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You are free to bring evidence. Though yes, Skylake manages to fit the uncore in ~24mm^2, but with separate PCH.Quad Core + PCH + 128bit DDR-4 should be not more than 100mm2
You have a point here, even if "only need" is a little strong of a statement.You have to take-off Polaris 128bit GDDR-5 memory controllers (16-20mm2), you only need the DDR-4 on the CPU. So the die comes down to ~100mm2
Man, Polaris taught you nothing.HBM2 will be used as a common L4 cache as AMD APUs support a single address space. CPU and GPU can share pointers. This is only possible with a design where HBM2 is a high bandwidth cache. AMD Vega's High bandwidth cache controller is a dead giveaway that this is the design of the future.