New Zen microarchitecture details

[Glo.]

Anyone else finds odd that in the CPU-Z leak, the benchmark is in an English OS, while the CPU-Z pic is in Chinese?

Taken with a different camera too, judging by the pic size.

Good catch.

 

[Doom2pro]

If it's a fake it would explain why the OPN has it at 3.7/3.3 @ 65W when those models at those clocks are supposed to be 95W TDP, looks like a possible oversight in another fake?

 

[CatMerc]

Well, we have already had 1 fake from Chinese, time to increase salt levels.

brb going to AMD subreddit and saying RX 460 is very poorly priced.

 

[lolfail9001]

brb going to AMD subreddit and saying RX 460 is very poorly priced.

Farming downvotes there is my prerogative.

If it's a fake it would explain why the OPN has it at 3.7/3.3 @ 65W when those models at those clocks are supposed to be 95W TDP, looks like a possible oversight in another fake?

Not unlikely, though that CPU-Z screen is i think legitimate, actually.

 

[inf64]

I'm looking for some known Zen OPN codes to test my decode script.

For now I have those here:

ZD3601BAM88F4_40/36_Y
ZD3201BBM4KF4_34/32_Y
ZD3301BBM6IF4_37/33_Y
ZD3406BAM88F4_38/34_Y

If you have others, please post them here or PM me.
Thanks!

Hint for the "unknown" number in OPN.
ZD3301BBM6IF4_37/33_Y

The number is written right next to the base clock number.

 

[Dresdenboy]

I'm well aware that ZEN is a clean sheet design, but i don't think any drastic changes to the die will be present in the first refresh.

Looking more closely, you might see, that the basic coarse core layout from Nehalem to Kaby Lake didn't change that much. If you loosen the filter a bit, this might go back till Banias or P!!!. But until SKL, there were, of course, significant changes to the die from gen to gen. Same for K7 to K10/Husky (Llano).

But design methods changed over time. Zen has a lot of synthesized blocks. Somewhere I read, that they tested lots of floorplan variants. It might simply be easier than before to change the layout more significantly. So depending on the uarch changes, the core floorplan might change significantly. Still a lot of the present stuff would remain the same, e.g. the uop$, the integer ALUs, and special units like IDIV.

If you're speaking about the whole die, then yes, it might be, that a lot would be taken over (still the same sockets on DT/server platforms), but the CCX blocks might change more in the core areas. This could also require some stretching of the die.

 

[Dresdenboy]

Hint for the "unknown" number in OPN.
ZD3301BBM6IF4_37/33_Y

The number is written right next to the base clock number.

The base clock actually uses 3 digits for Zen ES.

 

[inf64]

The base clock actually uses 3 digits for Zen ES.

Yeah but the point still stands. Just connect the dots

 

[CatMerc]

Yeah but the point still stands. Just connect the dots

Oh just say it you tease

 

[Doom2pro]

This picture says it's a "Model Revision Number" whatever that is.

 

[inf64]

This picture says it's a "Model Revision Number" whatever that is.

Yes it does say that but that doesn't mean it is correct.

 

[Sven_eng]

Oh just say it you tease

Literally connect them The numbers are 1 and 6.

 

[inf64]

Well you have base clock and then you have 1. What could it be? You now know it is not revision number or anything like that.

 

[swilli89]

Well you have base clock and then you have 1. What could it be? You now know it is not revision number or anything like that.

I'm assuming the "1" is how many Intel supporters per CPU sold have crawled back into the darkness? A linear 1:1 relationship I'm assuming. Could be wrong..

 

[Doom2pro]

In the production OPNs it's mostly letters, X for X models (XFR most likely) and B for Business (PRO) models, 0 for the rest and I have only seen 1 used in the qualification samples, my guess meaning locked base clock, turbo and/or XFR disabled.

 

[Dresdenboy]

Well you have base clock and then you have 1. What could it be? You now know it is not revision number or anything like that.

One sample had a "5" at this spot IIRC.

 

[inf64]

One sample had a "5" at this spot IIRC.

Yep 5 is not that much now that we know specs of say 1800X . It has 4Ghz Turbo clock and 3.6Ghz base, almost there .

 

[CatMerc]

Literally connect them The numbers are 1 and 6.

XFR clocks up to 6.1GHz on the stock cooler?

 

[Dresdenboy]

Yep 5 is not that much now that we know specs of say 1800X . It has 4Ghz Turbo clock and 3.6Ghz base, almost there .

BTW I connected the dots and got a circle!

OK how about turbo boost delta?

Edit: Delta in 50MHz or 100MHz steps?

 

[inf64]

BTW I connected the dots and got a circle!

OK how about turbo boost delta?

Edit: Delta in 50MHz or 100MHz steps?

You did good . Delta is always a big n1ce round number.
Nice avatar btw

 

[CatMerc]

You did good . Delta is always a big n1ce round number.
Nice avatar btw

Looking at these:

ZD3601BAM88F4_40/36_Y
ZD3201BBM4KF4_34/32_Y
ZD3301BBM6IF4_37/33_Y
ZD3406BAM88F4_38/34_Y

I don't see how it can be a turbo delta?

 

[inf64]

Looking at these:

I don't see how it can be a turbo delta?

Who said it was ST to base delta?

 

[CatMerc]

Who said it was ST to base delta?

Are you implying all core Turbo delta?

 

[inf64]

Are you implying all core Turbo delta?

You can check at what clock the images from Chinese leak showed 6C ES running during benchmarks. It will be evident.

 

[inf64]

So we have new leaked R15 numbers from Alva(?) guy again (boy if it was him he is in trouble :S). Benchmark ran with the same 6C/12T ES, 3.3/3.7Ghz with 3.4Ghz ACT meaning the MT test was ran at 3.4Ghz. Of course take everything below with a grain of salt - it is still fun .


Let us compare with XV/SB-E/IB-E/HSW-E and BDW-E

Source:
https://www.reddit.com/r/Amd/comments/5uu91c/ryzen_5_1600x_33ghz_cinebench_r15_benchmark/
Zen 6C/12T ES 3.3(3.4Ghz)/3.7Ghz
ST @ 3.7Ghz (ST Turbo) 146
MT @ 3.4Ghz (ACT) 1130-1140 (source baidu, same as for ST, both now deleted)
Both tests on 3.4Ghz would yield: ST 134 and MT ~1135(mean)

ST->MT scaling :
1135(mean)/134=8.45x => 8.45/6=1.4x or 40% SMT gain




Carizzo (Excavator) X4 845 3.5Ghz (base)/3.8Ghz (ST Turbo)
ST @ 3.8Ghz ~92
MT @ 3.5Ghz (base) ~314
Both tests on 3.4Ghz would yield: ST 82 and MT 305

ST->MT scaling :
305/92=3.71 => 3.71/2=1.86 or 85% scaling with CMT



i7-3930k SB-E 6C/12T 3.2Ghz base/ 3.8Ghz ST turbo
ST @ 3.8Ghz (ST Turbo)133
MT @ 3.5GHz (ACT) 907
Both tests on 3.4Ghz would yield: ST 119 and MT 881

ST->MT scaling :
881/119=7.4=> 7.4/6=1.23 or 23% SMT gain




i7-4930K IB-E 6C/12T 3.6Ghz base/4Ghz ST turbo
ST @ 3.9Ghz (ST Turbo) 140
MT @ 3.6Ghz (ACT) 959
Both tests on 3.4Ghz would yield: ST 122 and MT 905


ST->MT scaling :
905/122=7.42 => 7.42/6=1.23x or 23% SMT gain




5960x HSW-E 8C/16T 3(3.3Ghz ACT)/3.5
ST @ 3.5Ghz (ST Turbo) 140
MT @ 3.3Ghz (ACT) 1337
Both tests on 3.4Ghz would yield: ST 136 and MT 1377

ST->MT scaling :
1337/136=10.12 => 10.12/8=1.26x or ~26% SMT gain



5820K HSW-E 6C/12T 3.3(3.4Ghz ACT)/3.6Ghz
ST @ 3.6Ghz (ST Turbo) 140
MT @ 3.4Ghz 1025
Both tests on 3.4Ghz would yield: ST 132 and MT 1025

ST->MT scaling :
1025/132=10.72 => 7.76/6=1.29x or 29% SMT gain



6900K BDW-E 3.2Ghz(3.5Ghz ACT)/3.7Ghz (Anandtech bench)
ST @ 3.7Ghz 153
MT @ 3.5GHz ACT 1547
Both tests on 3.4Ghz would yield: ST 140 and MT 1502

ST->MT scaling :
1502/140=10.72 => 10.72/8=1.34x or 34% or 34% SMT gain



From above we can try and see what is Zen's IPC in R15 compared to:

1) XV
ST: 134/82=1.63x or 63% higher ST IPC for Zen Vs XV
MT (IPC+SMT): (1135 *4/6)/305~=2.5x or 2.5x higher throughput core for core; if we think of the XV module in terms of a "core" than 1C/2T on Zen is having 25% higher throughput than XV 1M/2T. Results usually do not scale upwards perfectly when upping the core count so adding 0.95 penalty gives us ~18% higher throughput than XV module and 2.37x vs XV core.


2)SB-E
ST: 134/119=1.126 or around 12-13% higher ST IPC for Zen Vs SB-E
MT(IPC+SMT): 1135/881=1.29x or 29% higher throughput than SB-E core


3)IB-E
ST: 134/122=1.1 or around 10% higher ST IPC for Zen Vs IB-E
MT(IPC+SMT): 1135/905=1.25x or 25% higher throughput than IB-E core


4)HSW-E (8C/16T 5960x)
ST: 134/136=0.98 or around 2% lower ST IPC for Zen Vs HSW-E
MT(IPC+SMT): (1135*8/6*)/1377=1.09x or 9% higher throughput than HSW-E core. Note that at 3.4Ghz 16T HSW-E has 34% higher throughput than 12T HSW-E, meaning R15 scales almost perfectly from 6 to 8 cores with SMT.


5)BDW-E
ST: 134/140=0.957 or around 5% lower ST IPC for Zen Vs BDW-E
MT(IPC+SMT): (1135*8/6)/1502=1.007x or about equal throughput for Zen Vs BDW-E core


edit reason:fixed XV MT scaling which was incorrect