Kaveri unerdelivered pretty much. Carrizo promissed far less and ended overdelivering a bit.
I feel completely the opposite. For example the APUs released after Trinity are something I previously would never have thought someone would actually release to the market.
With Steamroller a huge amount of features which are either not fully working or completely broken / missing, stuff that doesn't work as documented, etc. It's like someone pulled the plug on the project and many parts of the design were left incomplete, broken or untested. The situation improved quite alot in Carrizo / Bristol Ridge, but even they still contain some silly errors.
IIRC Trinity was the last project which had John Bruno as the chief engineer. It might be a coincidence, but Trinity is IMO the very last AMD design which is fully functional.
I think it's more likely because Trinity is the last APU that AMD thought might actually be competitive. At some point after the Piledriver architecture, AMD's R&D pipeline was flushed; the original plans for Steamroller and Excavator were canned, and what we got under those names were basically hacked-together stopgaps. There's a reason why AMD never even bothered to make HEDT or server chips for anything past Piledriver.
In other words, AMD's best CPU/platform engineers have all been working on Zen for the past couple of years, and the holdover construction core products got the "B" team.
having had a kaveri desktop/laptop long term and a carrizo laptop currently, I will tell you that kaveri was a great piece of kit.
Sorry for picking this up late, but I still had that tab open.
Did you see the different scores at different TDP settings? I think, the consensus so far was, that while discussing CMT or SMT scaling, we left out power constraints and turbo modes. Constant clock frequency tests were ideal. With the P3DNow! data I get 73% (CB15) and 79% (CB11.5).
At least a module penalty is heavier than most expected especially those who still believe it's dual core.
I would be happy to hear that people who worked on Hounds, Stars, Bulldozer, Piledriver and Cat cores also worked on Zen. It's the people who worked on Steamroller and Excavator who should be keelhauled, flogged and then banned working on semiconductors for life.
I'm sure it was because of bad management and organization, not the engineers. Many brilliant ideas don't make it to design/volume production, or are left incomplete. Only reason that AMD is not making good CPUs is because they have bad attitude towards things.It's interesting you should mention that because the rumors I heard some years ago was that AMD had stripped their main team from the construction cores and put Steamroller and Excavator into the hands of a team mostly dedicated to power efficiency.
I believe the core designs for SR and XV were already figured out, so you had bits left dangling as the best talent went to work on Zen and Zen+ under Keller.
I agree, I couldn't be happier with my Kaveri. For the money I put into it, and the versatility it offers, I can't complain about any aspect of it. I wonder if there is any technical reason they couldn't have offered an 8 core, iGPU less version of this for the FM2+ platform? In theory that would have outperformed the FX line. I think it would have done well for them as a holdover until Zen.
Kaveri was a pretty good chip, don't understand how you came to this conclusion that it is "sad".
We've got the 40% IPC increase claim for Zen over XV. I often heard the question, whether this is about per thread (ST) or per core throughput. I think, your example gives a good datapoint, as the microarchitectural+architectural changes seem to be much less than between XV and Zen. Yet there is a 30% IPC increase for the 2-threaded core over the 1-threaded one, without adding lots of execution ressources, large increases in L1 B/W, etc. (even latency went up from 3 to 4).Well, depends on the test and how it's run. From my own tests with Povray, I got a 5% IPC increase (1 thread per core) or 30% IPC increase (2 threads per core) over Core 2.
I'm sure it was because of bad management and organization, not the engineers. Many brilliant ideas don't make it to design/volume production, or are left incomplete. Only reason that AMD is not making good CPUs is because they have bad attitude towards things.
btw, your avatar is so scary
What did they a reasonably good job of doing was covering up the flaws in Kaveri. It did have some serious problems that still dog its users today. Pointless throttling and poor configurability of the memory controller (stuck @ DDR3-2400) are the two most glaring flaws.
Well (And this applies to Stilt's complaints too) whilst these are valid complaints in isolation, I think for the target market it's a non issue to be honest.
jhu, let me quote you from another thread here:
We've got the 40% IPC increase claim for Zen over XV. I often heard the question, whether this is about per thread (ST) or per core throughput. I think, your example gives a good datapoint, as the microarchitectural+architectural changes seem to be much less than between XV and Zen. Yet there is a 30% IPC increase for the 2-threaded core over the 1-threaded one, without adding lots of execution ressources, large increases in L1 B/W, etc. (even latency went up from 3 to 4).
More here and here.
So I question any claims, that the 40% number is only achieved with SMT.
This will be one of my next topics to work on.Dresdenboy, can you elaborate how this applies in the case of XV's 1 module versus Zen's 1 core and the implications of Zen's performance?
Again, bits & chips
http://www.bitsandchips.it/52-english-news/6815-speculations-about-zen-after-our-april-s-fool
They were right before on many occasions, but forum users will always neglect that. There is much more reason to believe in words of Fottemberg about this. You have to digest which is info he provides and which is his speculation(Fabbing process).
This will be one of my next topics to work on.
I'm skeptical about their Zen speculation. The freq/W given is extremely optimistic.
I'm skeptical about their Zen speculation. The freq/W given is extremely optimistic. And the claim that 2x128-bit FPU is a simplification vs 1x256-bit makes no sense. Fewer but wider SIMD units are simpler and use less power, area, etc for the amount of work done. That's the entire point of SIMD.
What are some of these many occasions Bits and Chips was right before? nVidia's interposer? The impression I get is that they could be a lot like Charlie at SemiAccurate: some legitimate sources and leaks but poor interpretation and analysis.
i was agreeing with youitsmydamnation, I'm not making an argument that there aren't reasonable tradeoffs between 128-bit and 256-bit SIMD, or that the latter is always preferable. Simply saying that what Bits and Chips stated, that 2x128-bit is simpler than 1x256-bit, is nonsense
As far as i know bulldozer never fused together its 128bit units, but executed the two 128 bits back to back for 256bit ops, unless you mean something else.The instruction set was even designed with this in mind, eg by not having full shuffles. So I never really got what Bulldozer's SIMD "fusing" was supposed to amount to.
i was agreeing with you
As far as i know bulldozer never fused together its 128bit units, but executed the two 128 bits back to back for 256bit ops, unless you mean something else.