All is in the second slide of Aten Ra s post, FTR dynamic power was measured at 0.880V, wich tell us that at this voltage everything is perfect, they wouldnt use value that would crush the metrics, wouldnt they..?..
Beside if it cant do 1V it would be a first in the industry, dont count on such irrationnal theories..
That's not IDS values there or TEV details
http://electroiq.com/chipworks_real_chips_blog/2014/12/18/iedm-monday-was-finfet-day/
You'll see many process metrics there... Intel has been releasing the best process metrics by far for many years. In fact, they are assumed to be nearly 1.5 nodes ahead of every competitor, such is their advantage. TSMCs 10nm will only be a little better than Intel's 14nm. Did you see 15% higher frequency, 2x lower power at 10% lower voltage? Did we see Intel get such huge power and frequency gains with 14nm finFET?
http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf
No they didn't. It is heat/power limiting the chip frequencies and scaling.
Also, cells used, the chip layout/design and PVT factors are crucial... Process variations modeled by IBM for its 14nm SOI show Ion is strongly affected by Vt and Hfin variations:
http://userweb.eng.gla.ac.uk/xingsheng.wang/ppt/ESSDER2012_A4L-E_WANG_final.pdf
Powerpoint process metrics does not equal actual complex logic implementations. Nor are those graph readings as simplistic as some AnandTech bar chart.
Static DC curve tracing with a FET doesn't even account for the biggest problem three terminal devices face, self-heating. Nor well known electron mobility drop-offs typically described as traps. And that is precisely what the shrinks past 65nm have been targeting. The focus to multicore didn't arise because it's more powerful. No, it arose from research that suggested it was the best way to tackle power/thermal problems and continue scaling.
A process showing "100% lower power" on the curves you're looking at means little in actual chip implementations, other than how the performance of a similar transistor compares.
The achievement of finFET was to keep a level of high performance with low power but it also comes with a handicap. FinFETs are worse at dissipating heat than planar and you tend to accrue heat build up around the fins.
Oh, IBM POWER9 is using GF 14nm HP
http://www.theregister.co.uk/2016/04/07/open_power_summit_power9/
I wonder why they didn't use LPP?
It seems pretty clear what the Red Team+ member is saying. It seems to me that you are just attacking juanrga because you don't like him.
Not a quotable person, at all.
The limitation is in the transistor power dissipation, if shrinked 1.4x they will have 2x less area, so their perf/watt should be increased by 2x if you want to operate them at same frequency.
Intel s 14nm didnt improve much their perf/Watt compared to their 22nm, i once stated it ad nauseam but seems people are keeping using them as if they were the end of all, 14nm LPP work at lower voltage for the same frequency, so the individual transistors dissipation will be less in a square proportion of the voltage, that s physics laws and is not much subject to any debate set apart correcting absolute values of various parameters.
See above. That's also not how semiconductor physics works. You can see it explained thoroughly in the IBM paper.
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