To be more accurate, it doesn't hint at a high frequency design à la BD. Since NHM Intel also uses 4 cycles. But at least it hints at a FinFET design achieving more than say 3 GHz at reasonable voltages. Jaguar has a 3 cycle latency and reaches 2.2GHz @ 28nm while being a LP design without not too much custom logic.
A fatter core can have very different causes. But here we're talking about fast transistors (14/16nm FinFET) in a not so dense process (20nm). Creating a 20-25 FO4 design would ease the timing pressure to use leaky transistors for critical paths. Maybe XV already went into that direction as it's already a heavily synthesized design, allowing for an easier change of target pipeline stage delays.
Here is an illustration of the possible benefits: