No you said based on 480 clocks, clocks for Zen doesn't look good.
Clocks and power consumption are parts of the same thing, they made architectural decisions based on hitting a perf/watt metric for mobile discrete for Polaris. Architectural decision will either enable or inhibit clock rate this will be just as much around target circuit timings as it is higher level architectural decisions.
The question that remains is how much different in perf/watt clock scaling could a AMD GPU be if targeted from group up to hit that ~150watt mark. We will have to wait until Vega to really see.
Why does everyone wanting to shit on Zen's clocks ( mostly because they can't find a uarch reason to do so) constantly ignore actual CPU's (mongoose and Kyro) clocks on LLP remember these cores are ~50% wider then CON/CAT / ~25% narrower then Zen.
Even
A57 on LPE is 1.6watts a core @ 2.1ghz. A57 is significantly wider in execution then Zen because Zen has multiple RFP's and schedulers vs 57's shared scheduler/dispatch. While Zen is wider in Decode/retirement. A57's a ~15 stage pipeline for int, Zen will be longer then that ( i think around 20 stages) so even that will allow for higher clock ceiling vs a A57.
Serious, even stilt has said CON core says FMAX limited by the L2 ( its the horrible module cache design). Take a new cache system, take Excavators front end, take a new execution stage and take Excavators load/store stage. Its not magically going to become a clocking dog, people here are basically saying 14nm LPP is worse then 28nm bulk.............