Ok makes good sense. I guess amd also had to design with less timing pressure when they dont have the same control of proces as Intel have?
Ok makes good sense. I guess amd also had to design with less timing pressure when they dont have the same control of proces as Intel have?To be more accurate, it doesn't hint at a high frequency design à la BD. Since NHM Intel also uses 4 cycles. But at least it hints at a FinFET design achieving more than say 3 GHz at reasonable voltages. Jaguar has a 3 cycle latency and reaches 2.2GHz @ 28nm while being a LP design without not too much custom logic.
A fatter core can have very different causes. But here we're talking about fast transistors (14/16nm FinFET) in a not so dense process (20nm). Creating a 20-25 FO4 design would ease the timing pressure to use leaky transistors for critical paths. Maybe XV already went into that direction as it's already a heavily synthesized design, allowing for an easier change of target pipeline stage delays.
Here is an illustration of the possible benefits:
The irony here is hilarious.....
Overclocked 980 Ti is also at least 20% and more faster than overclocked Fury X, which justifies the higher TDP. Also, 980 Ti isn't using a liquid based cooler, which lowers the TDP..
Anyway, back on topic. I really hope Zen performs well. An AMD slot A Athlon CPU was my first self built PC, so I have a soft spot for AMD and I want them to succeed.
We need them to succeed otherwise the stagnation of the market will continue.
Intel bought the market with illicit tactics in the mid 2000's. What makes you think they wouldn't just do the same thing again?
They've tried doing that in mobile and failed.
Any weakness will be exploited with community benchmark obsession, too, no matter how questionable the relevance of the benchmark is.XV already has support for FMA3/AVX2, and presumably Zen will have the same. XV suffers pretty badly under AVX2, though, and my impression was that the major reason for that was its requirement that it split instructions in hardware before executing them. Maybe I'm wrong in my reasoning. All I know is that AVX2 code doesn't handle much better than the same code optimized for SSE3 instead when run on XV.
Zen is going to run into a bunch of AVX/AVX2 code optimized for Intel processors with 256-bit FMACs. If it can't handle that any better than XV then I'll be rather disappointed.
It seems they mostly care when it's a fanboy talking point. When Nvidia was dominating with GTX 480s and 580s there was complaint (mostly just in the tech press articles) about heat and noise but also more people bragging about their SLI 480 setup — and articles about triple 480 SLI.To be honest, I'm not interested in a 95 watt part. And I'm getting more than a little sick of people who are. Since when did enthusiasts care about wattage?
Good on Zen for having the latency advantage, but FMA (particularly FMA3) is going to be the issue I was driving at earlier. XV already has support for FMA3/AVX2, and presumably Zen will have the same. XV suffers pretty badly under AVX2, though, and my impression was that the major reason for that was its requirement that it split instructions in hardware before executing them. Maybe I'm wrong in my reasoning. All I know is that AVX2 code doesn't handle much better than the same code optimized for SSE3 instead when run on XV.
Zen is going to run into a bunch of AVX/AVX2 code optimized for Intel processors with 256-bit FMACs. If it can't handle that any better than XV then I'll be rather disappointed.
Let's wait and see. A lot of people in the Zen team came from the cat core team. They didn't do bad on AVX, so they shouldn't with AVX2 on Zen as there is also enough integer SIMD execution hardware. Just look at how Jaguar did vs. Excavator in these examples:Good on Zen for having the latency advantage, but FMA (particularly FMA3) is going to be the issue I was driving at earlier. XV already has support for FMA3/AVX2, and presumably Zen will have the same. XV suffers pretty badly under AVX2, though, and my impression was that the major reason for that was its requirement that it split instructions in hardware before executing them. Maybe I'm wrong in my reasoning. All I know is that AVX2 code doesn't handle much better than the same code optimized for SSE3 instead when run on XV.
Zen is going to run into a bunch of AVX/AVX2 code optimized for Intel processors with 256-bit FMACs. If it can't handle that any better than XV then I'll be rather disappointed.
1798 AVX :VADDPS ymm, ymm, ymm L: 1.47ns= 3.0c T: 0.98ns= 2.00c
1799 AVX :VMULPS ymm, ymm, ymm L: 0.98ns= 2.0c T: 0.98ns= 2.00c
1800 AVX :VMULPS+VADDPS ymm, ymm, ymm L: 2.44ns= 5.0c T: 1.02ns= 2.08c
1801 AVX :VMULPS ymm1.. VADDPS ymm2.. L: 1.47ns= 3.0c T: 0.98ns= 2.00c1798 AVX :VADDPS ymm, ymm, ymm L: 2.39ns= 5.0c T: 0.48ns= 1.00c
1799 AVX :VMULPS ymm, ymm, ymm L: 2.39ns= 5.0c T: 0.48ns= 1.00c
1800 AVX :VMULPS+VADDPS ymm, ymm, ymm L: 4.77ns= 10.0c T: 0.95ns= 2.00c
1801 AVX :VMULPS ymm1.. VADDPS ymm2.. L: 2.39ns= 5.0c T: 0.95ns= 2.00c1798 AVX : VADDPS ymm, ymm, ymm L: 1.81ns= 4.0c T: 0.23ns= 0.50c
1799 AVX : VMULPS ymm, ymm, ymm L: 1.81ns= 4.0c T: 0.23ns= 0.50c
1800 AVX : VMULPS+VADDPS ymm, ymm, ymm L: 3.62ns= 8.0c T: 0.40ns= 0.88c
1801 AVX : VMULPS ymm1.. VADDPS ymm2.. L: 1.81ns= 4.0c T: 0.45ns= 1.00cThe problem with good 256bit AVX/AVX2/FMA performance is you need 256bit paths. And that's a TDP killer. Without these paths my 6700K could maybe have been sold as a 55W TDP CPU.
Same reason why AVX512 is server only.
If Zen gets these 256bit paths, then it will be clocked at 3Ghz or below for 8 core parts.
I explained before, that AMD likely evaded this option and chose to add decoders, fpu pipelines, caches, etc. as additional full cores instead. The discussion above was about execution efficiency pitfalls of construction cores. They're not only limited by not having 256b paths.The problem with good 256bit AVX/AVX2/FMA performance is you need 256bit paths. And that's a TDP killer. Without these paths my 6700K could maybe have been sold as a 55W TDP CPU.
Same reason why AVX512 is server only.
If Zen gets these 256bit paths, then it will be clocked at 3Ghz or below for 8 core parts.
I explained before, that AMD likely evaded this option and chose to add decoders, fpu pipelines, caches, etc. as additional full cores instead. The discussion above was about execution efficiency pitfalls of construction cores. They're not only limited by not having 256b paths.
Some computing tasks need high throughput (over all cores). Here both more cores or wider paths can help. Other tasks (e.g. raytracers) need shorter latencies and higher ILP (e.g. not so perfectly well parallelizable code with lots of short, partly independent serial paths).
I am not really interested in the deeply technical discussion going on in this thread. All i know is my next cpu upgrade will be sometime next year. So between i3-6100 and Zen quad core APU whichever has better performance will get my money. If the $120 Zen APU has igpu that's atleast as fast as an r7 250x and cpu performance atleast as good as Haswell i3 then that should be enough for me to consider Zen.
I am not really interested in the deeply technical discussion going on in this thread. All i know is my next cpu upgrade will be sometime next year. So between i3-6100 and Zen quad core APU whichever has better performance will get my money. If the $120 Zen APU has igpu that's atleast as fast as an r7 250x and cpu performance atleast as good as Haswell i3 then that should be enough for me to consider Zen.
Any weakness will be exploited with community benchmark obsession, too, no matter how questionable the relevance of the benchmark is.
If Zen doesn't do AVX2 well, expect the "definitive" benchmark to use it relentlessly. Hopefully Keller was smart enough to realize that the only way to compete with Intel is to copy their designs as much as possible because otherwise there is room for selective benching (like running FP-heavy benches when comparing Intel with FX chips and mostly ignoring integer). It looks like he got the hint by going to SMT.
Let's wait and see. A lot of people in the Zen team came from the cat core team. They didn't do bad on AVX, so they shouldn't with AVX2 on Zen as there is also enough integer SIMD execution hardware. Just look at how Jaguar did vs. Excavator in these examples:
Moar cores wont be any better than AVX/FMA. if you cant bundle them in AVX/FMA, you cant really do much better with moar cores either.
I think we are looking at (if there was 8C/16T) IB-E level of performance
Any weakness will be exploited with community benchmark obsession, too, no matter how questionable the relevance of the benchmark is.
If Zen doesn't do AVX2 well, expect the "definitive" benchmark to use it relentlessly. Hopefully Keller was smart enough to realize that the only way to compete with Intel is to copy their designs as much as possible because otherwise there is room for selective benching (like running FP-heavy benches when comparing Intel with FX chips and mostly ignoring integer). It looks like he got the hint by going to SMT.