Code:
Architecture Branch Misprediction Penalty
AMD K10 12 cycles
AMD Bulldozer 20 cycles
Pentium 4 (NetBurst) 20 cycles
Core 2 (Conroe, Penryn) 15 cycles
Nehalem 17 cycles
Sandy Bridge 14-17 cycles
Source:
http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2
Zen's pipeline won't be as short as K10's. And it doesn't need to be, as improved branch prediction plus some (rumoured) additions like checkpointing (before taking a hardly predictable branch), µOp cache, SMT (run the other thread at higher IPC in the meantime) reduce the perceived cost of mispredictions.
Some AMD patents show the cycles, for example US20140025933:
MAP, RDY, SCH, XRF, EX0, [EX1..], RE0, RE1, RE2 (Seronx, did you get the 3 retire stages from this patent?)
Before that there should be IT0, IT1/IC0, IT2/IC1-ICn, DEC0-DECm (parallel BP?) (see US20150121050).
That adds up quickly. If you compare those parts to Jaguar with a 14 cycle branch misprediction penalty, it looks to be at least as long for Zen, if not longer.
Of course, more stages could be required for the added units and increased complexity (wider schedulers, FMA support, checkpointing, SMT, etc.).