New Zen microarchitecture details

[NTMBK]

When readin this website, i read about the ZEN lite core.

http://vrworld.com/2016/05/11/amd-confirms-sony-playstation-neo-based-zen-polaris/



Now since the new ps4 apu will have 8 cores, this to me sounds that the SMT capabilities will be removed. For they may or can never be used. What else could be removed from such an 8 core cpu to match the 8 jaguar cores from the current ps4 ?

I mean, the goal is to stay compatible with the old jaguar cores to be able to run existing software. And make the apu as cheap as possible.
I am sure that the os from the ps4 hides the clock differences and other architectural changes from the games. I assume that the games are not programmed in a "bare metal" sense.

To be honest, it sounds like VR World are making stuff up.

 

[William Gaatjes]

To be honest, it sounds like VR World are making stuff up.

Ok, i will just wait and see as usual. :|
I feel like a watcher from the marvel universe.

 

[NostaSeronx]

Nosta, how is your love affair with FD-SOI going? It's been a long time since you wrote something about it.

Better than ever... If AMD ever releases a design on 22FDSOI it would be a powerhouse.

A lot of things have been done on 28FDSOI that could be pushed down to 22FDSOI.

If you design on any FDSOI node, 6T SRAM becomes your de-facto memory design;
16T CAM? Do 6T SRAM. 5x(?) area shrink
10T CAM? Do 6T SRAM. 2.5x(?) area shink
8T SRAM? Do 6T SRAM. 1.4x(?) area shrink

Having issues with FIVR efficiency with Adaptive DVFS[AVFS]?
Switched DC-DC Capacitors can solve that. Different designs but largely you would be looking at 88.5% to 95.5% efficiency. Compared to some in product designs that go from 60% to 77%.

Now look at Bulldozer;
Bulldozer use three Vts on 32nm/28nm; LVT, RVT, HVT.

LVT is primarily used in critical paths, RVT in varying degrees of channel length for everything else, and HVT in analog.

22FDSOI gives 5 Vts if you go full suite; sLVT, LVT, RVT, HVT, ULL.

LVT to sLVT+FBB, RVT-nominal to LVT+FBB, RVT-memory stays RVT-memory w/ RBB, RVT-long could stay RVT with RBB+PB or HVT with RBB. Analog can be a mix of HVT and ULL. HVT-Analog w/ RBB for critical analog, ULL-Analog w/ RBB for everything else, etc.

I don't know the overdrive for 22FDX-UHP. So, can't really tell you exact measure of how fast Bulldozer on 22FDSOI could be. The design in EDA would have to be re-architected to get the complete benefits anyway.

FBB can increase frequency or lower active power consumption.
RBB can increase temperature tolerance or lower standby power consumption.

It wouldn't be surprising to see a successor to the FX-9590 @ 140W with a Tj_max of 100*C rather than 61*C. FDSOI is several times more heat tolerant than PDSOI/FinFET/Bulk anyway.

 

[Unoid]

Better than ever... If AMD ever releases a design on 22FDSOI it would be a powerhouse.

A lot of things have been done on 28FDSOI that could be pushed down to 22FDSOI.

If you design on any FDSOI node, 6T SRAM becomes your de-facto memory design;
16T CAM? Do 6T SRAM. 5x(?) area shrink
10T CAM? Do 6T SRAM. 2.5x(?) area shink
8T SRAM? Do 6T SRAM. 1.4x(?) area shrink

Having issues with FIVR efficiency with Adaptive DVFS[AVFS]?
Switched DC-DC Capacitors can solve that. Different designs but largely you would be looking at 88.5% to 95.5% efficiency. Compared to some in product designs that go from 60% to 77%.

Now look at Bulldozer;
Bulldozer use three Vts on 32nm/28nm; LVT, RVT, HVT.

LVT is primarily used in critical paths, RVT in varying degrees of channel length for everything else, and HVT in analog.

22FDSOI gives 5 Vts if you go full suite; sLVT, LVT, RVT, HVT, ULL.

LVT to sLVT+FBB, RVT-nominal to LVT+FBB, RVT-memory stays RVT-memory w/ RBB, RVT-long could stay RVT with RBB+PB or HVT with RBB. Analog can be a mix of HVT and ULL. HVT-Analog w/ RBB for critical analog, ULL-Analog w/ RBB for everything else, etc.

I don't know the overdrive for 22FDX-UHP. So, can't really tell you exact measure of how fast Bulldozer on 22FDSOI could be. The design in EDA would have to be re-architected to get the complete benefits anyway.

FBB can increase frequency or lower active power consumption.
RBB can increase temperature tolerance or lower standby power consumption.

It wouldn't be surprising to see a successor to the FX-9590 @ 140W with a Tj_max of 100*C rather than 61*C. FDSOI is several times more heat tolerant than PDSOI/FinFET/Bulk anyway.

Since IBM gave fabs and tech to GF, will we see a modified 14nm FDSOI?

 

[Dresdenboy]

14LPP vs. 22FDX:

 

[monstercameron]

14LPP vs. 22FDX:

So finfet has lower power at the same frequency, however fdsoi can achieve much lower frequencies and voltages. What about cost of implementation?

 

[The Stilt]

SOI is cheaper than FinFet. Significantly easier to manufacture.

 

[Phynaz]

So finfet has lower power at the same frequency, however fdsoi can achieve much lower frequencies and voltages.

Be careful of making broad generalizations from one data point.

 

[maddie]

Be careful of making broad generalizations from one data point.

What one data point?

Aren’t those Frequency / Power curves on the graph?

 

[ShintaiDK]

What one data point?

Aren’t those Frequency / Power curves on the graph?

They are, for an A7 ARM core. Not how other designs may turn out.

 

[Exophase]

So finfet has lower power at the same frequency, however fdsoi can achieve much lower frequencies and voltages. What about cost of implementation?

If it simply had a lower Fmin you'd expect just one curve. It looks like the low power curve involves a different implementation that allows a much lower maximum frequency.

I think they're shortchanging the FF graph anyway, most little core implementations I've seen have Fmin at well below 800MHz. If you extend that 14FF graph out to the left the 0.4V 22FDX graph doesn't look nearly as impressive.

The whole thing is kind of weird anyway. 520MHz 0.4V 22FDX uses 92% less power than 800MHz 28nm? Why make that comparison instead of 800MHz with 22FDX or 520MHz with 28nm?

 

[monstercameron]

If it simply had a lower Fmin you'd expect just one curve. It looks like the low power curve involves a different implementation that allows a much lower maximum frequency.

I think they're shortchanging the FF graph anyway, most little core implementations I've seen have Fmin at well below 800MHz. If you extend that 14FF graph out to the left the 0.4V 22FDX graph doesn't look nearly as impressive.

The whole thing is kind of weird anyway. 520MHz 0.4V 22FDX uses 92% less power than 800MHz 28nm? Why make that comparison instead of 800MHz with 22FDX or 520MHz with 28nm?

And now I have a migraine

So focusing on the perf/watt curve of the main fdsoi process it has no benefits over ff save for costs...
Stilt/exo/dresden what about die size, density and other such variables?

Also, at a glance...wouldnt that special low power process be interesting in a gpu like product?

 

[Abwx]

If it simply had a lower Fmin you'd expect just one curve. It looks like the low power curve involves a different implementation that allows a much lower maximum frequency.

The implementation is strictly the same, it s just that in this case the transistor body is polarised with a voltage...

I think they're shortchanging the FF graph anyway, most little core implementations I've seen have Fmin at well below 800MHz. If you extend that 14FF graph out to the left the 0.4V 22FDX graph doesn't look nearly as impressive.

But you cant extend it, at least not meaningfully since minimal voltage is 0.6V for LPP...

The whole thing is kind of weird anyway. 520MHz 0.4V 22FDX uses 92% less power than 800MHz 28nm? Why make that comparison instead of 800MHz with 22FDX or 520MHz with 28nm?

They did it, at 520Mhz 28nm is at 180mW while 22FDX is at 20mW, 14 LPP should be at 60mW since it can no more scale voltage below 0.6V.

 

[frozentundra123456]

What one data point?

Aren’t those Frequency / Power curves on the graph?

Yea, they are "curves", in the same sense that one completed pass makes a quarterback a super bowl champion.

I sure would like to see the regression equation for those single point graphs. And even the graph which has two points has a curved fit, which is impossible for only 2 points.

 

[el etro]

I would love to benchmark the performance of IBM14 SOI Finfet process, will be ready soon at GF and maybe allowed to fab others chips with it. All presentations that i see so far indicates it performs the same as Bulk Finfet, but with a small higher cost. Would be nice if SoiFF does better than 14LPP at high-performance aplications, it could be used to fab AMD CPUs and GPUs.

 

[The Stilt]

Implementing SOI on FinFet should lower the manufacturing cost, not increase it. Unless of course the labour / machine time is significantly cheaper than usual.

 

[Abwx]

Yea, they are "curves", in the same sense that one completed pass makes a quarterback a super bowl champion.

I sure would like to see the regression equation for those single point graphs. And even the graph which has two points has a curved fit, which is impossible for only 2 points.

May i suggest to first study what it is about before doing random assumptions.?.

Why should there be regression equations since these are continous power/frequency curves..?.

As for not being straight lines is it surprising when knowing that frequency scale as a....power function of power, that is, about a degree 2 polynomial, a parabole if you prefer, so 2 points are indeed not enough to trace such figures..

Below minimum voltage theses will be straight lines because only frequency can be reduced, so power will down scale accordingly, that is linearly this time...

 

[Phynaz]

And now I have a migraine

So focusing on the perf/watt curve of the main fdsoi process it has no benefits over ff save for costs...
Stilt/exo/dresden what about die size, density and other such variables?

Also, at a glance...wouldnt that special low power process be interesting in a gpu like product?

If it were great every fab would be using it. 99% of the chip market has left FDSOI behind.

 

[NostaSeronx]

14LPP vs. 22FDX: http://i.imgur.com/99eFuce.png

So finfet has lower power at the same frequency, however fdsoi can achieve much lower frequencies and voltages. What about cost of implementation?

At some point the 9T FinFET (GF14LPP) will become less efficient than 12T FDSOI(GF22FDX). (Vdd across is 0.8v, no overdrive)

 

[ksec]

28FDSOI doesn't yield, and is capacity constrant compared to other node. It is cheaper to implement, nartual extention in terms of cost. But you are limited to a relatively few and unclear upgrade path. 22 FDSOI isn't ready yet. TSMC 16nm FFC and 3rd Gen 14nm from Samsung will likely be cheaper and offer path forward.

Which means 28FDSOI cost proposition offers extremely attractive value for IoT or other SoC where performance isn't in need of constant upgrade. And have a longer life time before redesign.

 

[William Gaatjes]

The implementation is strictly the same, it s just that in this case the transistor body is polarised with a voltage...

But you cant extend it, at least not meaningfully since minimal voltage is 0.6V for LPP...



They did it, at 520Mhz 28nm is at 180mW while 22FDX is at 20mW, 14 LPP should be at 60mW since it can no more scale voltage below 0.6V.

That is interesting. If i interpreted it correctly, when forward biasing, the transistor can switch fast at low voltages, and with applying reverse biasing while the transistor is not used, it can be shut down entirely with just a few pA of leakage. That could make for some very interesting energy efficient cpu.

 

[Dresdenboy]

Regarding 22FDX area:

20% smaller die than 28nm bulk planar

DDR3/DDR4 mem controllers and other IP is possibly still under development, according to the slides:
http://www.soiconsortium.org/fully-...design-for-fd-soi-2015/Kengeri 22FDX 0915.pdf

It's not useful for Zen anyway:

 

[Abwx]

That is interesting. If i interpreted it correctly, when forward biasing, the transistor can switch fast at low voltages, and with applying reverse biasing while the transistor is not used, it can be shut down entirely with just a few pA of leakage. That could make for some very interesting energy efficient cpu.

With Foward biaising the transistor is working like any other transistor, it is fast but require a high voltage and has high leakage.

When reverse biaised the transistor conduct (read switch faster) better at very low voltage, what is accomplished is equivalent to lowering the transistor threshold voltage (Vth), hence it start to switch robustly at lower voltages.

With higher voltages reverse biaising is not relevant since it would increase leakage tremendously, not counting other non wanted effects.

The advantage is to set electricaly some transistors threshold voltage while with usual geometries and designs the threshold voltage is fixed at the manufacturing level and cant be changed later, hence different transistors are used depending of the usage while with 22FDX a kind can be enough for several usages.

It's not useful for Zen anyway:

To the contrary, it is relevant since it is displayed that 14nm LPE was already adequate for high frequencies/high perfs chips, 14nm LPP should fit the usage even better..

 

[Dresdenboy]

To the contrary, it is relevant since it is displayed that 14nm LPE was already adequate for high frequencies/high perfs chips, 14nm LPP should fit the usage even better..

I see 22FDX only spanning the lowest 2 categories.

 

[William Gaatjes]

With Foward biaising the transistor is working like any other transistor, it is fast but require a high voltage and has high leakage.

When reverse biaised the transistor conduct (read switch faster) better at very low voltage, what is accomplished is equivalent to lowering the transistor threshold voltage (Vth), hence it start to switch robustly at lower voltages.

With higher voltages reverse biaising is not relevant since it would increase leakage tremendously, not counting other non wanted effects.

The advantage is to set electricaly some transistors threshold voltage while with usual geometries and designs the threshold voltage is fixed at the manufacturing level and cant be changed later, hence different transistors are used depending of the usage while with 22FDX a kind can be enough for several usages.

Ah, okay. Thank you. I thought that the future designed cpu was going to be able to dynamically change the bias voltage depending on the workload. That way controlling power consumption of different sections of the cpu cores / soc. My mistake.