New Zen microarchitecture details

[sirmo]

The thing is that it is not possible to achieve it even as a peak. Unless a peak is defined as few nanoseconds. That's around the time it takes for the power management to lock the CPU frequency to 3.00GHz after the iGPU is utilized.

Yeah I don't think they even test that stuff. It's just a calculated value. At least when it comes to GPUs there is a formula for it. I think it's #SP * 2 * frequency.

 

[The Stilt]

Yeah I don't think they even test that stuff. It's just a calculated value. At least when it comes to GPUs there is a formula for it. I think it's #SP * 2 * frequency.

Yeah. As soon as I gave some feedback about it a "note" emerged to the slides showing these claims:

"Theoretical GFLOPs calculated by AMD as 856 for AMD A10-7850K with AMD Radeon R7 Series Graphics. GFLOP = CPU GFLOPS + GPU GFLOPS = CPU Core Freq (3.7GHz) x Core count (4) x 8 + GPU Core Freq (720MHz) x Radeon Core (512) x 2"

Theoretical or not, it is just as impossible ever to achieve...

 

[majord]

this may go some way to explaining cache density



I assume this is for 16nmFF, Anyone have insight? If true it would explain a much more dense L3

 

[Vortex6700]

That would be illegal. So no...

Yes, because intel has been deterred that way before....

It doesn't matter what amd produces (i7 4960 ipc w/16 cores @ $100/65watts) it will only sell until intel doesn't want it to anymore.

 

[LTC8K6]

More IPC claim craziness:
Feb 2016 pres: still 40% uplift, with footnote:


Now there is this at Computerbase as an answer to the reddit/current IR slide:

(I instantly saw the different font sizes and placing)
http://www.computerbase.de/2016-05/amd-prozessor-bristol-ridge-zen/

"expected"?

Why expected at this point?

 

[Dresdenboy]

"expected"?

Why expected at this point?

No SKU definitions. They might have to watch the yield and binning and possibly want to adapt to Intel's offerings later this year. Maybe BR leaked early because CZ (same die) was already known and defined.

 

[guskline]

I know this discussion happened months back but the whole overclockers dream thing was always about the cooling and power delivery. They never stated that it would overclock high. I just think it is dishonest to bring up that quote and misconstrue as him saying the fury x would overclock high.

Sorry, but I watched, re-watched and re-re-watched the entire presentation of the Fiji launch including the discussion by the 3 panelists- one of whom was Joe Macri.

He said what he said AND never said, OH I mean the AIO cooler is an Overclocker's dream.

I chock it up to an over-exuberant statement that just wasn't born out at all. He probably got caught up in the excitement of the moment.

I owned and still own R9 290s -Stout cards but hardly an overclocker's dream. The heat issue is true, thus I have them custom watercooled.

The AIO system on Fiji (let's not talk about the pump problems and potential patent infringement) was good but why brag about cooling and power delivery when Fiji doesn't appear to have a ton of overclocking room? It just doesn't make sense.

However to stay on track about ZEN in this thread, I think the apparent lock down on information "might" have a bit to do with what I perceive to be Dr. SU's no nonsense attitude of bringing solid defensible products to market that can stand on their own merits. This bodes well for AMD.

 

[LTC8K6]

No SKU definitions. They might have to watch the yield and binning and possibly want to adapt to Intel's offerings later this year. Maybe BR leaked early because CZ (same die) was already known and defined.

Hard to believe that AMD doesn't have this info already and doesn't know what the ipc improvement over excavator will be at this point.

"expected" seems odd to me.

 

[The Stilt]

I find it slightly disturbing that the original slide (with "40% IPC improvement") has suddenly dissappeared from AMDs site :sneaky:

 

[Arachnotronic]

I find it slightly disturbing that the original slide (with "40% IPC improvement") has suddenly dissappeared from AMDs site :sneaky:

It's still there, AMD investor presentation.

 

[Dresdenboy]

Hard to believe that AMD doesn't have this info already and doesn't know what the ipc improvement over excavator will be at this point.

"expected" seems odd to me.

Maybe this is just cautionary speak.

And I talked about 2 data points - yield/binning and Intel offerings. So does AMD have the latter?

 

[senseamp]

I find it slightly disturbing that the original slide (with "40% IPC improvement") has suddenly dissappeared from AMDs site :sneaky:

No Y-axis labels on the right side, could basically be anything

 

[coercitiv]

No Y-axis labels on the right side, could basically be anything

It's not anything, it's throughput: that expected 40% IPC uplift plus whatever SMT brings to the table puts an 8 core Zen at ~1.7x throughput vs. a 4 module Excavator. They just couldn't resist screwing with the perceived Y axis values so that it seems 2x.

For those of you who want to see the presentation, page link for Investor Relations is here, and pdf is here. Slide 13 also states the following about Zen:

Over 40% improvement in IPC over current AMD CPU core

 

[Exophase]

It's not anything, it's throughput: that expected 40% IPC uplift plus whatever SMT brings to the table puts an 8 core Zen at ~1.7x throughput vs. a 4 module Excavator. They just couldn't resist screwing with the perceived Y axis values so that it seems 2x.

There's also SMT bonus on top of that, assuming that that wasn't a factor in the 40% number. And isn't the 40% number vs Excavator, not Bulldozer?

Going from Bulldozer to Zen could be something like 1.25 (BD -> EX) * 1.4 (EX -> Zen) * 1.2 (non-module scaling) * 1.2 (SMT bonus) = 2.52

That would be if Zen and BD are at the same clock speed. Which I doubt; there's a reason why AMD has been promoting IPC improvement and not ST performance. So maybe a 2x value works for some highly threaded workloads on an 8C16T Zen.

I still don't think that the graph is supposed to have a non-zero base. Yes the scale seems to be different from the other one but scale is completely irrelevant for a relative graph, so long as they're both linear.

EDIT: Wait, they changed that slide from Orochi to Excavator and slightly adjusted the dimensions? Okay, I think it's pretty safe to say that someone doesn't know what they're doing.

 

[ElFenix]

:hmm:

 

[Arachnotronic]

:hmm:

I just downloaded it from the link and it still has the 40% bit and it compares to Carrizo.

 

[dark zero]

Ok... wondering if AMD makes the Conroe Miracle and delivers a brutal ammount of improvement. A miracle like that could start a revival on the PC market.

 

[krumme]

Ok... wondering if AMD makes the Conroe Miracle and delivers a brutal ammount of improvement. A miracle like that could start a revival on the PC market.

You will see tons of ipc improvement. When was the last time you saw 40% plus smt? In that sense its a bigger miracle than p4 to conroe.
There is just one catch. The competitor is not a "phenom" but a damn fine product. Lol. Makes the miracle pale quite a bit.

Its not easy to be the small guy in class.

 

[ElFenix]

I just downloaded it from the link and it still has the 40% bit and it compares to Carrizo.

that one was from upthread where dresdenboy got us back on topic (post #1230), and was the first one i saw. no idea if it was the original.

 

[Dresdenboy]

that one was from upthread where dresdenboy got us back on topic (post #1230), and was the first one i saw. no idea if it was the original.

AMD has both slide decks online, one linked from their archive I think. I included both links on my blog.

 

[csbin]

http://www.chip-architect.com/news/Zen_Summit_Ridge_First.jpg

 

[majord]

Hard to believe that AMD doesn't have this info already and doesn't know what the ipc improvement over excavator will be at this point.

"expected" seems odd to me.

I think you'll find "expected" is in relation to performance. IPC does not = performance , and as mentioned shipping clock speeds would depend on yeilds, final stepping Fmax, etc, etc.. Minimum 5 months out from now before they ship.

IPC on avg would indeed be locked down at this point, unless they find some late bug during validation., but it would have to be pretty severe.


PS is it a goo idea to be hot linking Han's images? his host might get hammered.

 

[krumme]

Hans interpretation is here
http://semiaccurate.com/forums/showpost.php?p=263145&postcount=2754

Same size as 8c xeon D - 160mm2 ? Cheap consumer xeon comming up then

 

[The Stilt]

Hans interpretation is here
http://semiaccurate.com/forums/showpost.php?p=263145&postcount=2754

Same size as 8c xeon D - 160mm2 ? Cheap consumer xeon comming up then

Didn't Dresdenboy have exactly the same estimation?

I bet Zeppelin is larger than that. Afterall it has 2MB more L2 and 4MB more L3 than Broadwell-DE. Also SRAM is less dense on 14nm LPP than on Intel's low power process variant, regardless if they are HP or HD cells.

 

[IntelUser2000]

I am feeling like AMD's situation vs. Intel in CPUs parallels their situation vs. Nvidia in GPUs. Expectation too.

It certainly doesn't PAY to speculate. D: