New Zen microarchitecture details

[KTE]

Are you sure that this is just a matter of the used process?

I'm only pointing to what can/does happen even with good cores, process and lofty performance previews [1] when power plays wreck havoc.

[1] = http://www.anandtech.com/show/9837/snapdragon-820-preview/2

Sent from HTC 10

 

[Justinbaileyman]

They already have haven't they? Wasn't that the Carrizo chips which were in some HP laptop (EliteBook 755 G2/3) products last year? Or was that 6th gen? The Bristol Ridge is just suppose to be Carrizo in desktop format still on .28nm is it not?

Pretty sure you are correct, but these Bristol Ridge APU's aren't going to be 2c/4t this time right?
Pretty pretty sure the slides released last month said 4c/8t with revised 8c Igpu and the chips would be running 65w tdp.Or was that an April fools Joke?

 

[DrMrLordX]

Bristol Ridge will all be 2m/4t.

 

[coffeemonster]

Bristol Ridge is pretty much carizzo on proper desktop socket with functioning igpu. I don't believe they were ever planned to be more than just 2 module 4 thread chips.

 

[KTE]

Can you show the link to the process?

The entire PC market is shrinking in volume anyway. 2015 was -10.6% YoY (IDC). Projections were for -4.5%... Q1 down 9.6% QoQ already (according to Gartner).

Lenovo taking top spot and increasing its share. No shocker, as their Thinkpads and X1C are phenomenal and have a huge (growing) fanbase in the enterprise markets.

HPE EMEA has a lot of internal political rife going on so I expect them to start tanking. They've culled most of their expert staff in the past year, and it's hurting them big time.

Sent from HTC 10

 

[Dresdenboy]

The Stilt, any thoughts on this regarding AM4 load line requirements?

Seen here: https://semiaccurate.com/forums/showthread.php?p=264074#post264074
Source: http://videocardz.com/60686/watch-amd-computex-polaris-update-live-stream-here

 

[Dresdenboy]

The entire PC market is shrinking in volume anyway. 2015 was -10.6% YoY (IDC). Projections were for -4.5%... Q1 down 9.6% QoQ already (according to Gartner).

Lenovo taking top spot and increasing its share. No shocker, as their Thinkpads and X1C are phenomenal and have a huge (growing) fanbase in the enterprise markets.

HPE EMEA has a lot of internal political rife going on so I expect them to start tanking. They've culled most of their expert staff in the past year, and it's hurting them big time.

Sent from HTC 10

And where is the link? That buyers are satisfied with smaller devices?

 

[csbin]

Noctua Readies AMD Socket AM4 Upgrade Kit

http://www.techpowerup.com/222983/noctua-readies-amd-socket-am4-upgrade-kit

Noctua is among the first CPU cooler manufacturers to develop a retention kit for the upcoming AMD socket AM4. There are three versions of this, compatible with all existing Noctua coolers, except D0 series and NH-L9i series. This means that even 10-year old heatsinks from Noctua should be able to cool next-gen AMD chips. Noctua will be giving these away for free to all existing customers (proof of purchase required).

 

[KTE]

And where is the link? That buyers are satisfied with smaller devices?

For a regular consumer, that's what the datashift is showing in simple terms. Maybe VR can buck this...

But it would be very simplistic to say just that, and as enthusiasts, that's always the biggest problem. Oversimplification

The point I'm struggling with is that from the instruction latencies/stages, Zen looks like a high frequency design... higher than BD. P4 was 20 stage and P4E a few stages more.

16 FO4 delays was POWER6 being 5-wide with SMT4, running 5GHz at 65nm and able to run upto 6.1GHz if required. Is that what AMD is aiming for?

If so, I don't understand this approach for today's markets. Especially not from JK.

Sent from HTC 10

 

[itsmydamnation]

The point I'm struggling with is that from the instruction latencies/stages, Zen looks like a high frequency design... higher than BD. P4 was 20 stage and P4E a few stages more.

No it doesn't, it looks like any other middle of the road x86 CPU maybe you need to go look at other CPU's. There is no information right now about how many stages Zen has, only execution time of instructions which is only a small percentage of the total pipeline. Also total number of stages is a maximum, The better you prefetch, predict and recover from mis predict the longer your front end can be while you reduce the length of time waiting on dependent instructions.

But looking at execution latencies it looks no different to any other 3+ghz x86 design. Hell given the fact it doesn't do FMA in a single unit like haswell+ its FP execution latencies are significantly lower then CPU's of recent history.

Many of the published patients were worked on when CON core was the target, which mean its just as likely they would be implemented into a shorter pipeline as they are to be implemented as described.

Personally i think Zen is going to share a lot in common with CON cores in terms of Front end and Load/store. With the execution/scheduling and the cache system seeing the big reworks, given that i expect a pipeline around CON core length. But thats rather irrelevant (unless it was extra short or extra long), wide aggressive OOOE processors live and die on having the right data as close as possible to the execution units as soon as possible.

 

[deasd]

The point I'm struggling with is that from the instruction latencies/stages, Zen looks like a high frequency design... higher than BD. P4 was 20 stage and P4E a few stages more.

16 FO4 delays was POWER6 being 5-wide with SMT4, running 5GHz at 65nm and able to run upto 6.1GHz if required. Is that what AMD is aiming for?

If so, I don't understand this approach for today's markets. Especially not from JK.

Sent from HTC 10

What sources made you think so? Very unlikely that AMD keep high FO4 delay and deeper stages in Zen, because Zen looks to be aimed for better ILP if Dresdenboy's diagram is closed to reality.

Power6 is not a reference here because RISC is different than CISC, there's not any hint you can find in Power or ARM or other ISA.

 

[Dresdenboy]

For a regular consumer, that's what the datashift is showing in simple terms. Maybe VR can buck this...

But it would be very simplistic to say just that, and as enthusiasts, that's always the biggest problem. Oversimplification

What we see is a mix of markets, desires, needs, products, processes, companies, strategies. A simple "14LPP is crap" doesn't explain this mix' behaviour, especially not the S7's success or that A9@14LPE seems to be more widely present than the TSMC variant according to polls.

The point I'm struggling with is that from the instruction latencies/stages, Zen looks like a high frequency design... higher than BD. P4 was 20 stage and P4E a few stages more.

16 FO4 delays was POWER6 being 5-wide with SMT4, running 5GHz at 65nm and able to run upto 6.1GHz if required. Is that what AMD is aiming for?

If so, I don't understand this approach for today's markets. Especially not from JK.

Zen's pipeline length might be between Jag and XV. While clock distribution gets more complicated and power hungry at higher clock frequencies, there might even be a lowish (2x) FO4 sweet spot defined by power/clock gating opportunities due to finer granularity. Maybe we'll learn more about that at this year's Hot Chips.

Also see what we discussed here a while ago:
http://forums.anandtech.com/showthread.php?p=38210064#post38210064

BTW:
http://fudzilla.com/news/processors/40784-amd-has-zen-ready-for-demo

 

[CentroX]

sources say that Zen will be shown at computex!!!!!

 

[dark zero]

sources say that Zen will be shown at computex!!!!!

Expected and the release date will be shown too.

Also that day is the official day Bristol Ridge appears on public and is being sold.

High chances to see Polaris 11 on the wild too.

 

[carop]

16 FO4 delays was POWER6 being 5-wide with SMT4, running 5GHz at 65nm and able to run upto 6.1GHz if required. Is that what AMD is aiming for?

POWER6 was a high-frequency IN-ORDER micro-architecture with a short 13-FO4 pipeline structure.

 

[ET]

Noctua will be giving these away for free to all existing customers

Very cool. Thanks for the heads up, although I have Arctic and Cooler Master.

Still, hopefully AMD will be shipping decent coolers from now on and so I won't need aftermarket coolers for my modest needs.

 

[Killrose]

Bummer about the new cooler requirement. I just bought a Zalman CNPS11 Extreme for my FX 8320e. It did allow me to go up an extra 200mhz however over the CNPS5 to 4.5Ghz and temps are still below the CNPS5.

But no socket 4 love? Bummer

 

[exar333]

So hoping we have a new 'Hammer' on our hands with Zen. Its been 10 years since AMD was in my gaming machine!!!

 

[DrMrLordX]

sources say that Zen will be shown at computex!!!!!

Let's hope so. They need something more at Computex than Bristol Ridge.

Bummer about the new cooler requirement. I just bought a Zalman CNPS11 Extreme for my FX 8320e. It did allow me to go up an extra 200mhz however over the CNPS5 to 4.5Ghz and temps are still below the CNPS5.

But no socket 4 love? Bummer

Agreed. That's the end of a looooong run of compatible HSFs. It was bound to happen eventually. Don't feel too bad, though; those of us with older Noctua heatsinks still need proof-of-purchase, and I definitely don't have that for my seven-year-old nh-d14.

 

[Phynaz]

The entire PC market is shrinking in volume anyway. 2015 was -10.6% YoY (IDC). Projections were for -4.5%... Q1 down 9.6% QoQ already (according to Gartner).

Lenovo taking top spot and increasing its share. No shocker, as their Thinkpads and X1C are phenomenal and have a huge (growing) fanbase in the enterprise markets.

HPE EMEA has a lot of internal political rife going on so I expect them to start tanking. They've culled most of their expert staff in the past year, and it's hurting them big time.

Sent from HTC 10

HPE has nothing to do with the PC.

 

[KTE]

Zen's pipeline length might be between Jag and XV. While clock distribution gets more complicated and power hungry at higher clock frequencies, there might even be a lowish (2x) FO4 sweet spot defined by power/clock gating opportunities due to finer granularity. Maybe we'll learn more about that at this year's Hot Chips.

Also see what we discussed here a while ago:
http://forums.anandtech.com/showthread.php?p=38210064#post38210064

Thanks for that link!

I'm a bit skeptic from what I've seen so far about this design. But we'll see. 2x FO4 delays would be K10/P3 territory (and one I could definitely see merit in).

Also Willamette starts at 20 stages but Prescott is approx 31. I still remember that bit Conroe 14 stages 19.5 FO4: https://books.google.co.uk/books?id=Pektbnxx6G4C&pg=PA77&lpg / http://cadlab.cs.ucla.edu/~cong/papers/main.pdf

I'd love to see how do they manage to abate parasitic capacitance if deeper pipelines (high frequency) are targeted.

POWER6 was a high-frequency IN-ORDER micro-architecture with a short 13-FO4 pipeline structure.

FO4 is arc/process. generic (looks at circuits).

But take POWER7/8 if that alone is a problem.

HPE has nothing to do with the PC.

It's a company wide problem now after the major culling, divesting and restructuring, altho it primarily affects their Workstation/Server... a lot of which they've just divested anyway.

What sources made you think so? Very unlikely that AMD keep high FO4 delay and deeper stages in Zen, because Zen looks to be aimed for better ILP if Dresdenboy's diagram is closed to reality.

Which diagram? Link please

BTW, More stages -> lower depth per stage... for high frequencies.

As D.Wang nicely explained some time back: http://www.realworldtech.com/fo4-metric/2/

Or http://people.duke.edu/~bcl15/teachdir/ece590_fall14/Presentation_Pritam.pdf

Sent from HTC 10

 

[sm625]

I just wish someone would leak a simple kraken 1.1 test result. I want to see 800mS. If they cant hit that then they may as well throw in the towel because at the rate apple is going they are going to hit that by fall of 2017, if not fall of this year! It would be a disgrace to get beaten by such a tiny core in benchmarks like this, but you can already see that this is going to be the case with the next apple SoC vs the FX8350. 40% on javascript just isnt going to do enough. That gets beat by a 5 year old celeron.

 

[inf64]

It would be a disgrace to get beaten by such a tiny core in benchmarks like this, but you can already see that this is going to be the case with the next apple SoC vs the FX8350. 40% on javascript just isnt going to do enough. That gets beat by a 5 year old celeron.

Well to be fair to AMD they did say "over 40% more IPC than EX core" which in turn means ~1.6x over PD. But we have no clue if this is average figure or not - my guess is that it is average from a number of ST benchmarks at same fixed clock.

 

[deasd]

Which diagram? Link please

'Which diagram'? LOL, you really don't know this thread was started by Dresdenboy. Go to 1 page and post count 1. (hard to believe people replying without reading title and contents from start)

BTW, More stages -> lower depth per stage... for high frequencies.

This is true but AMD will not make anything similar to Netburst. You should take Sandybridge/Nehalem as reference compare to Zen this time. Arch with higher frequency doesn't mean it has to be like Netburst.

 

[Ajay]

'Which diagram'? LOL, you really don't know this thread was started by Dresdenboy. Go to 1 page and post count 1. (hard to believe people replying without reading title and contents from start)

Seriously? That's what is difficult with these large threads (1500+ posts!) - most people don't read them from the beginning.