ShintaiDK
Lifer
- Apr 22, 2012
- 20,378
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Im surprised by all this clock speed talk after the age of the MHz myth had long past.
Performance is still based on IPC*Clock.
Im surprised by all this clock speed talk after the age of the MHz myth had long past.
And AMD tends to have superior IPC than nVidia.Performance is still based on IPC*Clock.
Im surprised by all this clock speed talk after the age of the MHz myth had long past.
After Computex, how confident are people that Zen will be widely available for retail purchase in Q4 of this year?
40% performance increase. Yes.
40% on clocks based on process. No.
40% IPC. No.
Sent from HTC 10
40% performance increase. Yes.
40% on clocks based on process. No.
40% IPC. No.
Sent from HTC 10
7 months left in the year and they already shown that they have silicon that is clocking up to expectations. If anything I'm more confident now.
So are we discussing what WE THINK AMD really means or just what they are literally saying?10:55PM EDT - 8C/16T, AM4 Desktop, 40% more IPC
10:55PM EDT - Summit Ridge APU, video was on Zen silicon
10:54PM EDT - There's a chip on stage
10:53PM EDT - (early pre-alpha is my addition, I assume)
10:53PM EDT - Tapeout earlier this year, early pre-alpha qualification
10:53PM EDT - The industry needed a new high performance CPU
10:53PM EDT - Zen
Obviously reversed time - but AMD is sticking with 40% IPC increase, at least officially. I don't know what the official base is for this IPC increase. Zen is in pre-alpha - safe to say very early engineering samples. AMD isn't getting into any specifics.
12 stage pipeline and those design specs. Did it hit those targets at 65nm?RWT said:Barcelona is a 283mm2 design that uses 463M transistors to implement four cores and a shared 2MB L3 cache in AMD’s 65nm process. The SOI process uses 11 layers of copper interconnect with a low-k dielectric and dual stress liners and embedded SiGe for PMOS transistors. The device described at ISSCC was targeted at 2.2-2.8GHz at 1.15V, while operating within a 95W maximum thermal envelope. AMD claims that their 65nm process has a 15ps FO4 inversion delay, which suggests that Barcelona’s pipeline is just a little less than 24 FO4 delays.
But what we think they are saying is the tricky bit. PR always spins things, especially if the product is delaying or failing in any way... and AMDs PR spin doesn't have a good track record. I know they are saying 40% IPC but I'm willing to bet that 40% IPC really means 40% performance...
And even that - on average - is so rare a feat from one gen to another
I know they are saying 40% IPC but I'm willing to bet that 40% IPC really means 40% performance...
Personally, I think AMD has a lot to lose by raising expectations for a product they secretly know can't deliver on those promises. So I'm inclined to take their words at face value.
Remember that conroe had roughly 2x IPC compared to netburst. Zen will have 1.4x to Excavator, or 1.61 to PD (1.75x to BD). Also for intel Core Duo/Yoonah was in the middle, C2D had roughly 1.15 to 1.2x perf to original CD. Also remember, initial batchs of conroe on desktop saw lower clocks compared to late netburst, a fact ofter overlooked because performance was still good cause the massive ipc increase and the passage from 1c2t to 2c2t. With COn->Zen this will be quite different.They said 40% IPC in an investor relations meeting. If they really meant 40% performance increase, yet said IPC increase, all the investors who lose money can sue them for that money, after which the key officials go to prison. The United States has bad consumer protection laws, but really solid investor protection laws. This is the source of modern corporate speak, which tries to not make clearly false statements while misleading as much as possible. "40% IPC" is the opposite of this. It means AMD believes that Zen will have 40% higher IPC, or the corporate lawyers would have prevented AMD from saying that.
But how did they not get sued for missing clock targets?
Because clocks are unknown until the CPUs are actually out of the assembly line. They are allowed to be wrong, so long as they can point out good reasons to believe as they did, and so long as they made it clear that they were estimates.
So what if they miss IPC targets like that?
IPC is not like clocks. You can find out the exact reached IPC of your CPU on any workload you want in simulation, well before the design goes anywhere near manufacturing. This is completely unlike clocks, which are becoming harder to estimate on new processes instead of less.
Getting 40% IPC increase from an iteration on design is extremely rare. Getting 40% higher IPC over your previous design when doing a completely new design is completely trivial. IPC is the result of many design choices you can pick. Within the limits of the available IPC in the workload, you can just choose to have x IPC and design a cpu that meets that goal. The statement "40% better IPC" is completely unambitious. It's something you can just choose to have.
So why don't everyone have crazy high IPC CPUs?
Because IPC is not performance. Performance is IPC * clocks, and all those design choices that give you more IPC are tradeoffs against clock speed. I could, in a few months, design you a CPU that had IPC not 40% greater, but 2 times greater, of BD. I could even implement it on a FPGA. It just wouldn't be worth anything, because it would have clock speed measured in kilohertz. Getting more IPC is not hard. What is hard, and costs billions in engineer time, is raising IPC*clocks.
Which ties us back to:
I don't think they have +40% performance in ST. They can have +40% IPC, but to do that they will have designed a wider, brainier core, which will naturally run at slightly lower clock speeds.
Historically, P4 chose to have less IPC in search of higher clock speeds. When this didn't work out due to excess heat, Intel designed Conroe instead, which decided to have less clock speed but more IPC. This worked out, because the IPC*Clock speed of Conroe was much higher than that of P4.
Bulldozer chose to have less IPC in search of higher clock speed. When this didn't work out, they designed Zen instead. Whether it is a success depends entirely on how much clock speed they had to trade for the IPC gains.
Seriously. Clock speeds are not the best metric when comparing chips from different generations and architectures.
The issue for them is that fans are raising expectations for them. 40% IPC is a simple statement, but a lot of people are reading it as 40% performance. If/when AMD fails to have 40% performance on ST loads, how many people will be disappointed?
I think part of the problem may be that AMD has not had a new cpu architecture for desktops for so long it's hard to compare to Excavator/Piledriver.
They said 40% IPC in an investor relations meeting. If they really meant 40% performance increase, yet said IPC increase, all the investors who lose money can sue them for that money, after which the key officials go to prison. The United States has bad consumer protection laws, but really solid investor protection laws. This is the source of modern corporate speak, which tries to not make clearly false statements while misleading as much as possible. "40% IPC" is the opposite of this. It means AMD believes that Zen will have 40% higher IPC, or the corporate lawyers would have prevented AMD from saying that.
Thanks I wasn't aware of that.Technically there is an Excavator-based Athlon out there that can be used for such a comparison, and I think user looncraz did just that.
Thanks I wasn't aware of that.
Personally, I think AMD has a lot to lose by raising expectations for a product they secretly know can't deliver on those promises. So I'm inclined to take their words at face value.