There is not enough bandwidth to include anything even remotely as powerful as RX 460. Raven will have < 47GB/s (maximum officially supported) of shared bandwidth while RX 460 has 96GB/s of dedicated bandwidth. You could include such GPU, but it would be nothing but a waste of power mostly.
It would be strange, but not damaging, as a SMT thread has ~65% the performance of a single thread on a single core, while a CMT thread performs at roughly ~80% when sharing the module.That would be a pretty damaging way for them to measure it.
As for the 16B fetch window, that was just a random size chosen by me. It all depends upon how deep the pre-decode logic can look for non-dependent instructions and how accurately it can predict branches. Smaller fetches simply make the task more difficult, but larger fetches are only useful if the hardware is fast and accurate enough to find non-dependent instructions that actually need to be executed.
U.S. Pat. No. 20150121050 said:[0045]
The IC pipeline is a three stage pipeline that can fetch 32 bytes of instruction data per cycle. Each address in the PRQ, depending on the predicted start and end location within the 64 byte prediction window, needs either one or two flows down the IC pipeline to forward all of the data to the DE.
L1d has as least 4 cycles (see GCC patch -> +4 cycles delta for each load+ex op). Going to the FPU adds another 3 cycles.For their Last-Level Cache, Level-4 cache.
My speculation is;
64B L1i Fetch Window (AMD64 Variable-op)
2x4 AMD64 to Macro-op Decode (Same as Steamroller/Excavator)
16B or 8 Macro-op L0i Fetch Window (Internal Macro-ops, RISC-like)
3-cycle(simple load), 4-cycle(complex load); L1d
10-cycle; L2
52-cycle; L3 (L3 -> L2 => 64B vs Jaguars 16B)
52-cycles + 50 ns; L4
52-cycles + 100 ns; Memory
Misprediction to L1 BTB; ~18-cycles
Misprediction to L0 BTB/BTQ; ~9-cylcles
There is not enough bandwidth to include anything even remotely as powerful as RX 460. Raven will have < 47GB/s (maximum officially supported) of shared bandwidth while RX 460 has 96GB/s of dedicated bandwidth. You could include such GPU, but it would be nothing but a waste of power mostly.
the 730 about ties with Kaveri APUs which only have 34GB/s but double the texture mapping units. A ZEN apu would have to be worse than Kaveri to not beat a GT 730.My 730 already has 40GB/s bandwidth.Aleast m expecting hd7770 performance in $120 APU otherwise the APU will be a flop.
Edit:Nevermind Zen APU will not come out until late next year.Best to go with Intel skylake/kabylake+discrete gpu.
the 730 about ties with Kaveri APUs which only have 34GB/s but double the texture mapping units. A ZEN apu would have to be worse than Kaveri to not beat a GT 730.
An APU without on chip memory (GDDR5, HBM) will never reach Xbone levels of performance. Xbone has almost 5 times more memory bandwidth than what any APU will ever have with two channel DDR3/4 memory. Bandwidth wise it's just not plausible. Sure you could put 4096 SPs on an APU to get insane amount of theoretical performance, but you'd always be bandwidth constrained if you do not have proper high speed on chip memory.What's more is that the Zen APU will be using GCN4 memory compression, so effective bandwidth will be higher still. Good caching could conceivably push performance to console level (well, XBox One level...), but it would be more likely to fall just shy of it.
My 730 already has 40GB/s bandwidth.Aleast m expecting hd7770 performance in $120 APU otherwise the APU will be a flop.
Quick question. The 40% IPC gain that AMD is claiming, is that for single threaded performance or multi-threaded?
An APU without on chip memory (GDDR5, HBM) will never reach Xbone levels of performance. Xbone has almost 5 times more memory bandwidth than what any APU will ever have with two channel DDR3/4 memory. Bandwidth wise it's just not plausible. Sure you could put 4096 SPs on an APU to get insane amount of theoretical performance, but you'd always be bandwidth constrained if you do not have proper high speed on chip memory.
XBox One actually only has 68GB/s of memory bandwidth which is then augmented by a small 32MB eSRAM cache. It has zero memory compression with 768 GCN 1.1 SPs running at 853Mhz. That's 'just' 1.23TFLOPS of total shader power.
AMD's new memory compression increases effective memory bandwidth about 18% over GCN 1.2, and about 35% over GCN 1.1, IIRC... at least when the data is compressible. All told, I'd hazard a guess of a net 20% bandwidth gain due to compression.
All that would suggest an effective bandwidth of ~48GB/s for Zen APUs- or about 70% of XBox One's DDR3 bandwidth. While that will hamper performance - we see that 4GB Polaris 10 doesn't get immensely hampered by having only 87.5% of the 8GB Polaris 10 bandwidth - only losing 3~5%. Losing another 10% or so from its max would just make the GCN4 performance closer to that of GCN 1.1 performance.
That only leaves the XBox One eSRAM cache is a notable advantage for that console over a theoretical Zen APU. If the top Zen APU has an L4 cache that advantage could vanish entirely.
Polaris 10 4GB has 38.4MB/s of dedicated bandwidth per GFLOP, while the 8GB model has 43.9MB/s. If Raven had RX 460 grade iGPU in it, it would have 18.7MB/s (at 2933MHz) of shared bandwidth per GFLOP. Even the GCN3 iGPUs (CZ/BR) are absolutely choked to death with their 41.7MB/s (at 2133MHz / 800MHz GEC) per GLOP shared bandwidth. And GCN3 has already very effective DCC.
Quick question. The 40% IPC gain that AMD is claiming, is that for single threaded performance or multi-threaded?
AMD initially only said IPC, but one other time (which I can't find right now) they specifically said 40% single-threaded IPC.
Multi-threaded performance should be slightly more than doubled (over Piledriver) with the same number of physical cores... at the same clock speed. Most likely, though, Zen will have a clock speed deficit.
Assuming a 700Mhz Zen deficit, Zen should have ~90% higher multi-threaded performance assuming 20% SMT scaling (per core). ~60% higher multi-threaded performance without SMT. And ~35% higher single threaded performance.
All of that is assuming a net 64% IPC improvement over Piledriver - or, specifically, FX-4350 at a fixed 4.2Ghz.
The claim was 40% IPC improvement for Zen core over a single XV core.
The claim was 40% IPC improvement for Zen core over a single XV core.
Which is practically meaningless without clock rates. When is AMD due to reveal more info? August?
At Hotchips, which is at the end of August.
Yes, which is about 64% over Piledriver :sneaky:
I like comparing with Piledriver because it has L3 and 8-core configurations.
Zen's architecture is very different.Looking at FX versus core i7 benches makes it look that is impossible for AMD to achieve the IPC of any Intel recent core.
If Zen doesn't do well in AVX 2 or whatever then expect the de facto community benchmark to lean heavily on it.
Looking at FX versus core i7 benches makes it look that is impossible for AMD to achieve the IPC of any Intel recent core.
TEST ZEN i7 4790K
Handbrake LQ 583 582.8
Handbrake 4K* 18.7 23.2
WinRAR 56.8 51.3
x265 4K 1.43 1.75
CB R15 ST* 137 181
CB R15 MT* 636 894
(LOWER IS BETTER)
Agisoft Stg1* 6.97s 5.57s
Agisoft Stg2* 7.75s 8.54s
Dolphin* 7.11s 6.8s
* Likely under-representative of Zen's performance improvements due to heavy reliance on areas drastically changed in Zen compared to the construction cores.HD 7770 (Cape Verde) has 10 GCN 1.0 CUs (640 shaders) running at 1000 MHz. The leaks so far indicate that Raven Ridge will have 11 CUs (704 shaders), presumably using the Polaris or Vega architecture. Even if the GPU clock speed was only 900 MHz, that should be about equivalent to Cape Verde in terms of raw compute power. Raven Ridge will only have about 65% as much memory bandwidth as the HD 7770, but the architecture changes between GCN 1.0 and Polaris should be able to make up for that deficit.
Based on what we know so far, Cape Verde-level performance sounds like a reasonable expectation.