Sorry if I misunderstood then. Hopefully this IS reminiscent of Haswell, that would be an incredible start to Zen's life.
Sorry if I misunderstood then. Hopefully this IS reminiscent of Haswell, that would be an incredible start to Zen's life.I think you're reading too much in my comment. This architecture reminds me of Haswell, that's all.
Whats your current estimate of diesize of a 8 core incl. L3?ComputerBase jumped the gun with HotChips slides:
https://www.computerbase.de/2016-08/amd-zen-architektur/
Between 160 and 200 mm².Whats your current estimate of diesize of a 8 core incl. L3?
What's the limitation of the process?Dresdenboy said:Between 160 and 200 mm².
Yeah, it's easy to see the word ripoff as a negative. It's actually a compliment.
What's the limitation of the process?
One source of the word riff is the music world, in which it's not uncommon for a musician to take a tune s/he has heard, and then perform a little variation on that tune. It happens all the time in some jazz sessions.
To "riff on Hamlet," then, would be for a person to take a line from the Bard and play with it, explore it, have some fun with it, look at it in various ways, explore it for levels of meaning and possible connections to other concepts and ideas, and so on.
we all can admit Intel probably found the best optimized way to do things and AMD is simply adopting the same techniques.
You're right. My brain substituted a common expression for an uncommon one. I'll try to read more slowly.I said "riff on" not "rip off."
The first two were due to AMD trying to adapt to Intel's changes concerning SSE5 specs, right?DrMrLordX said:but didn't thanks to stuff like FMA4, xOP, ST performance, blah blah blah.
AMD says the “breakthrough performance” of Zen can challenge Intel’s fastest processor to date — the 10-core Broadwell-# processor.
AMD said that power would be competitive, the frequency we saw would be even higher at production than what we saw, and production of what we saw could be produced at scale.
We'll have to wait for benchmarks, but I'm growing ever more suspicious that Zen's SMT implementation is more like Power8's than anything Intel's produced so far. Intel's approach has been to allow a second thread to use unused CPU resources, but doesn't really over-provision those resources (a single thread can very nearly saturate the whole CPU). On Power8, they can scale up to 8 threads per core (Zen will only do 2), but they make that viable by doubling down on key CPU resources in the first place (Instruction Cache, rename registers, etc.). The end result is that the second SMT thread on Intel increases overall performance by around 15-25%, but on Power8 the second SMT thread can increase overall performance by around 60% in some workloads. In Layman's terms, Power8's 'hyperthreads' are more useful than Intel's.
AMD haven't talked about rename registers yet, but they have revealed that the instruction cache is 64KB per core; perhaps not-so-coincidentally, that's double the size of Skylake's instruction cache, and the same size as Power8's. The L1 Data cache is only 32K in all of these processors, but its rather odd in processor design to have your instruction cache be twice the size of your L1 data cache -- unless you have a good reason. There's only two reasons I can think of -- either that second thread chews through a lot more instructions than in competing SMT designs, or possibly the uOp Cache can spill to L1. Looking at the slide from HotChips that shows which CPU resources are exclusive, competitively shared, or arithmetically arbitrated, has me leaning toward the former, though they might not have overprovisioned CPU resources enough to match Power8 fully. There were also rumors months back about Zen doing some really novel things with SMT, which would seem to back that up.
The implication of that would be that Zen could run at a lower clockspeed than Intel's current Broadwell DE but still match in overall threaded performance (but perhaps giving up 10-15% single-threaded performance (not clock-normalized)). For the mainstream, they could release a quad-core CPU at similar clocks to Skylake, and outperform it in threaded workloads. In gaming workloads, since current consoles make 6-7 threads available to games, a quad-core Zen with 4 hyper-threads giving ~60% additional performance would give a lot bettter performance than a quad-core i7 with 4 hyper-threads giving ~20% additional performance. In fact, that Zen would would have a throughput comparable to 6-7 dedicated cores.
We won't know until someone does an architecture deep-dive or we have benches showing SMT gains much larger than intel's. But its looking increasingly likely from what I see.
Yes,that part is a given,but performance figures in conclusion are bit over the top.He forgets that Power is SMT4,ofcourse,firing 2nd thread gives huge boost in performance.But I partly agree with him that L1-inst is unreasonably as 2 times large as L1-data, this is very similar to Excavator, and even Bulldozer has 64:16 ratio of L1 inst/data, which have much more resources and even dedicated pipeline for another 'thread'.
Sheduler per pipe still baffles me.Is this their solution for handling SMT?Anyone have any idea?
Thank you!The architecture of the schedulers has no impact on SMT. At that point, the uops coming in are already effectively anonymous -- the schedulers don't know or care from which thread they are from.
Having many 1-way schedulers has one big disadvantage -- each uop is assigned to scheduler on dispatch, and each scheduler can only execute one op per clock. Imagine a situation like:
1: add eax, ebx
2: add ecx, eax
3: add edx, eax
both 2 and 3 depend on the result of 1, but are independent of each other. If they all get assigned to a single scheduler, this piece of code takes 3 cycles to run, while a monolithic scheduler could run 2 and 3 simultaneously on different execution units. This disadvantage is not as bad as it sounds, as the simple solution of just spreading workload evenly across the queues is optimal most of the time. It does occasionally lose a cycle or two to scheduling losses, though.
The main advantage is that they are much easier to make larger, easier to clock higher and use less power. Intel Haswell has 60-entry scheduler that is shared between all instruction types. Zen has 6x14 entry for integer, plus unannounced separate queue for FP. The total Zen scheduler window is likely even bigger than the 97-instruction Skylake.
The separate schedulers should be fine, as this simplifies the design, allows higher frequencies, and saves power. And integer/AGU ops usually have low latencies, so that each scheduler doesn't need to look at too many ops to fill a latency induced gap. FP instructions have longer latencies, thus the FPU has a unified scheduler.Sheduler per pipe still baffles me.Is this their solution for handling SMT?Anyone have any idea?
Edit: Or the high level diagram is confusing me?
Yes,I am aware of that(with little help from Tuna-fish and yours,like your blog btw.and majord's diagram)now.My confusion was also from mix up in terminology;dispatcher-sheduler.The separate schedulers should be fine, as this simplifies the design, allows higher frequencies, and saves power. And integer/AGU ops usually have low latencies, so that each scheduler doesn't need to look at too many ops to fill a latency induced gap. FP instructions have longer latencies, thus the FPU has a unified scheduler.
Yeah, 3.75 GHz assuming perfect scaling. I wish AMD really had a choice for Foundry. Zen looks like an excellent achievement by AMD with the potential for some solid wins if marketing does it's job. But, having come this far, AMD really needs to be able to push uArch updates through quickly to maintain pace. That, and, GFL needs to ramp up it's 14nm process for higher clocks as well. It's allot to ask, but it sure would be nice to have a competitive choice in CPUs. Can't wait till 1Q17 to see real benchmarks!^Even with equal IPC and equal power usage, AMD would need a base 4GHz Zen to challenge Intels fastest in 2016.
Forget 2017.
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(Opinions are own)
It would be a bit more interesting - to say the least - if we got some info about the efficiency.
The writes about it is very slim imo in relation to its crucial importance.
Sous Blender, qui profite pleinement du multi-threading, Zen était légèrement devant tout en consommant un petit peu moins selon AMD