New Zen microarchitecture details

[KTE]

Just to add to this ( my job is designing data centre infrastructure) Zen has some really big opportunities because of 16 mem channels across 2P. This is because 32/64 GB LR-DIMM's are around 20/60 percent more expensive per GB then 16gGB RDIMM's. Your typical Enterprise VM farm is memory capacity, memory throughput and IO constrained long before CPU throughput constrained.

Most VM farms use middle of the road E5 Xeons ( depending which generation 10 to 16 cores etc) and even then you can normally get pretty aggressive in terms of CPU over subscription on CPU.

That's exactly my thoughts/experiences too... From the real corporate world.

Although I'm not naming names, it's against our Confidentiality Agreement to, but one major datacentre Corp to gov departments still has a few P4s and Clovertown based servers on. I can remember the exact one too -- X5355. I had to re-check 3-4 times when I saw it. Don't ask me why... but their 'refesh' is supposed to be this coming June->

Sent from HTC 10
(Opinions are own)

 

[Phynaz]

Gf announce 7nm
Pressrelease
http://www.digitimes.com/news/a20160919PR202.html
ramping h1 2018
Key paths ready for using euv

"Globalfoundries' new 7nm FinFET technology is expected to deliver more than twice the logic density and a 30% performance boost compared to today's 16/14nm foundry FinFET offerings, the company claimed"

Edit: ramp to risk production early 2018

Much better source here, somebody that was actually at the conference.

http://www.eetimes.com/document.asp?doc_id=1330467

 

[krumme]

Much better source here, somebody that was actually at the conference.

http://www.eetimes.com/document.asp?doc_id=1330467

How is that?
Loads of undocumented crap in either source as i can tell. I cant derive any new info but i am interested if any can do that from the smaller details and hints perhaps?

 

[Headfoot]

Gotta second what the data center guys are talking about. At the one I work with, CPUs are oversubscribed hard and memory / storage is more often the bottleneck. CPU speed > CPU cores because at least in a MS shop you pay licenses per physical core which easily outweigh the cost of the hardware itself. Even worse if you're an Oracle or SAP shop

 

[cdimauro]

Gf announce 7nm
Pressrelease
http://www.digitimes.com/news/a20160919PR202.html
ramping h1 2018
Key paths ready for using euv

"Globalfoundries' new 7nm FinFET technology is expected to deliver more than twice the logic density and a 30% performance boost compared to today's 16/14nm foundry FinFET offerings, the company claimed"

Edit: ramp to risk production early 2018

Moving from 16/14nm to 7nm should QUADRUPLE, not only double, the transistors density.

Much better source here, somebody that was actually at the conference.

http://www.eetimes.com/document.asp?doc_id=1330467

"Analysts agree Intel, the world’s largest semiconductor company, is still a step ahead of all comers with its process technology, but itrecently re-booted it’s still fledgling foundry operations. It is ramping a 10nm process now which some observers suspect will be the technical equivalent of 7nm nodes from Globalfoundries and TSMC."


Off-topic. This is about AMD, not Intel
Markfw900

 

[bjt2]

Moving from 16/14nm to 7nm should QUADRUPLE, not only double, the transistors density.

"Analysts agree Intel, the world’s largest semiconductor company, is still a step ahead of all comers with its process technology, but itrecently re-booted it’s still fledgling foundry operations. It is ramping a 10nm process now which some observers suspect will be the technical equivalent of 7nm nodes from Globalfoundries and TSMC."

They are only theoretically figures... For instance, passing from 28nm to 14nm increased about by 2.25x the density. I am not such expert to know the reasons, but this had happened before...

 

[leoneazzurro]

That's simply because while traditionally the process node was defined as half pitch of the smallest distance between identical metal elements, not all the devices scale down in the same way due to functional requirements. Also, you need to define interconnect areas that cannot be scaled down in the same way (if at all). So you cannot practically achieve the theoretical scaling according to the mere process node dimension.

 

[Dresdenboy]

They are only theoretically figures... For instance, passing from 28nm to 14nm increased about by 2.25x the density. I am not such expert to know the reasons, but this had happened before...

From my basic knowledge: Metal layers and contacted gate pitch affect density. The effective gate length is the actual number mostly related to the process "ID".

I assume that with given I/O, wire capacitance, dark silicon, and power/area density limits the focus shifted to Lg (affecting power and frequency), while using more expensive metal layers doesn't make sense.

 

[carop]

Moving from 16/14nm to 7nm should QUADRUPLE, not only double, the transistors density.

"Analysts agree Intel, the world’s largest semiconductor company, is still a step ahead of all comers with its process technology, but itrecently re-booted it’s still fledgling foundry operations. It is ramping a 10nm process now which some observers suspect will be the technical equivalent of 7nm nodes from Globalfoundries and TSMC."

First, the author of the article made several mistakes including die shrink, and has already updated his story.

Second, in order for that observation of the "analysts" to be true, Intel's N10 process technology should deliver a gate pitch about 45nm and a metal pitch about 30nm. Both pitches of Intel's N10 process fall short of these feature sizes.

I was expecting Intel to push lithography to deliver metal pitches somewhere around 32nm on its N10 process, but it did not enter quadruple patterning territory.

 

[KTE]

Moving from 16/14nm to 7nm should QUADRUPLE, not only double, the transistors density.

"Analysts agree Intel, the world’s largest semiconductor company, is still a step ahead of all comers with its process technology, but itrecently re-booted it’s still fledgling foundry operations. It is ramping a 10nm process now which some observers suspect will be the technical equivalent of 7nm nodes from Globalfoundries and TSMC."

Most 14nm out are technically half-node (16nm or even 20nm), as interconnects/BEOL are using older litho (28/22nm). That's why TSMC calls theirs 16nm. Intel is roughly FN to FN+HN ahead.

“Not all 10nm technologies are the same,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “It’s now becoming clear that what other companies call a ‘10nm’ technology will not be as dense as Intel’s 10nm technology. We expect that what others call ‘7nm’ will be close to Intel’s 10nm technology for density.”


The move to '7nm' is looong off due to costs. 14nm is going to be a long node, for sure.

"For many, it comes down to cost. For a 10nm chip, it takes $120 million for the design cost, plus 60% for the embedded software. In comparison, the total design cost is roughly $271 million for a 7nm chip, according to Gartner.

It will take chip designers about 500 man-years to bring out a mid-range 7nm SoC to production,” Gartner’s Wang said. Therefore, a team of 50 engineers will need 10 years to complete the chip design to tape-out. In comparison, it could take 300 engineer-years to bring out a 10nm device, 200 for 14nm, and 100 for 28nm, according to Gartner."

Compare the above to less than $30mill for a chip design at 14nm.

In 2007, 11nm node these firms forecasted to be shipping 21nm half-pitch chips by 2015. Right now, they are forecasting +40-50nm metal pitch. Intels 10nm gate pitch is 54nm -- far ahead of anyone else (hence why they've secured the mobile phone chip contracts - ARM).

So these FN shrinks are scaling at more like HNs, at best.


Edit: I lost the reference article... Will link here soon.

Sent from HTC 10
(Opinions are own)


Off-topic. This is about AMD, not Intel
Markfw900

 

[cdimauro]

So, long story short: the claimed 7nm are just marketing...

 

[KTE]

So, long story short: the claimed 7nm are just marketing...

But there is truth behind the PR... It's not just vacuous boasting.

Sent from HTC 10
(Opinions are own)

 

[cdimauro]

What kind of "truth"?

 

[leoneazzurro]

What kind of "truth"?

The truth is that transistor density WILL increase, only not by a factor of 4.

 

[cdimauro]

Of course. But talking about 7nm without getting a factor of 4 scaling from 16/14nm is a bit... excessive.

 

[KTE]

Of course. But talking about 7nm without getting a factor of 4 scaling from 16/14nm is a bit... excessive.

They don't really need a factor of 4. They just need the minimize their costs and be competitive.

They're all the same in the marketing regard.

Sent from HTC 10
(Opinions are own)

 

[Dresdenboy]

Of course. But talking about 7nm without getting a factor of 4 scaling from 16/14nm is a bit... excessive.

Did scaling become the only relevant metric?

 

[Masochrist_]

Technically, Samsung offers two different "types" of gate pitch (78 and 84, check the slides mid-page). At the end of the day, TSMC's and Samsung's processes aren't that far off dimensionally from Intel, and that difference might shrink in the future, when the focus goes from scaling purely down to finding new materials and techniques to improve performance.

It's not that far fetched to say that Intel has never had other foundries breathing on their neck like they have right now.

 

[FIVR]

In 2007, 11nm node these firms forecasted to be shipping 21nm half-pitch chips by 2015. Right now, they are forecasting +40-50nm metal pitch. Intels 10nm gate pitch is 54nm -- far ahead of anyone else (hence why they've secured the mobile phone chip contracts - ARM).

Uh, what mobile phone chip contracts would those be? From what I've seen over the last 10 years intel has performed dismally in mobile and the article you quoted is almost 100% counter-factual. What contracts are they even talking about? There isn't a single phone sold today by a major manufacturer that has an Intel SoC in it. In fact, there may not be any sold today period.

Also, if intel's density indicated a superior process then why does Apple continually chose TSMC to produce the iPhone SoC? If intel's process is superior, why are their own x86 chips an order of magnitude less efficient than ARM designs produced on "inferior" TSMCs process? Why is their top of the line server core showing lower IPC than Apple's mobile A10 offering? What will intel do when Apple can emulate x86 instructions fast enough to remove Skylake like they did with the IBM PowerPC 750?


Moreover, why are you posting intel marketing slides in a thread about AMD Zen? Are you just here to thread crap and push an agenda, along with your absurd marketing slides? Seriously I'd like some answers to these questions given the amount of FUD you've filled this thread with. Or you could just take your soap box elsewhere. Maybe VC&G where trolling is allowed.

 

[guskline]

In the development cycle of Zen, what is the AMD development team likely doing now?

I assume that a number of engineering samples are out and about but what is likely occurring and whenwill full scale production likely occur?

 

[The Stilt]

In the development cycle of Zen, what is the AMD development team likely doing now?

Evaluation / software related work mostly, but that's generally not done by the "development team". Co-processor firmwares, main software stack (AGESA), etc.

 

[bjt2]

Uh, what mobile phone chip contracts would those be? From what I've seen over the last 10 years intel has performed dismally in mobile and the article you quoted is almost 100% counter-factual. What contracts are they even talking about? There isn't a single phone sold today by a major manufacturer that has an Intel SoC in it. In fact, there may not be any sold today period.

Also, if intel's density indicated a superior process then why does Apple continually chose TSMC to produce the iPhone SoC? If intel's process is superior, why are their own x86 chips an order of magnitude less efficient than ARM designs produced on "inferior" TSMCs process? Why is their top of the line server core showing lower IPC than Apple's mobile A10 offering? What will intel do when Apple can emulate x86 instructions fast enough to remove Skylake like they did with the IBM PowerPC 750?


Moreover, why are you posting intel marketing slides in a thread about AMD Zen? Are you just here to thread crap and push an agenda, along with your absurd marketing slides? Seriously I'd like some answers to these questions given the amount of FUD you've filled this thread with. Or you could just take your soap box elsewhere. Maybe VC&G where trolling is allowed.

Actually Apple did it before with Rosetta technology. When it will have a competitive ARM CPU even in the desktop space (and indeed if the A9/A10 is a good custom chip, it can be clocked enough), it can do like the powerPC/x86 transition. Rosetta JIT translator for old software, fat binary for new softwares. It has yet all the software infrastructure...

 

[Phynaz]

In the development cycle of Zen, what is the AMD development team likely doing now?

I assume that a number of engineering samples are out and about but what is likely occurring and whenwill full scale production likely occur?

As The Stilt said there are many teams, not just one Zen team. So for example the teams that did things like logical design and floorplanning design will have moved onto other projects or have been disbanded. You'll have the testing and validation teams going full bore now, along with manufacturing and software teams along with others.

As far as full scale production, that depends upon your definition. AMD will have already placed orders for "production" wafers with Global Foundries. If you consider the fulfillment of those orders as full scale production then that would be determined by the delivery dates of those wafers. Since AMD isn't a manufacturer there really isn't the concept of full scale production.

Now if you're asking what is AMD's order schedule, that is information they aren't going to release. Wafers have to be ordered 6 - 12 months in advance for fab scheduling.

 

[cdimauro]

Did scaling become the only relevant metric?

Yes, if we talk about nanometers and transistor density.

Of course, a new productive process might bring other benefits.

Technically, Samsung offers two different "types" of gate pitch (78 and 84, check the slides mid-page). At the end of the day, TSMC's and Samsung's processes aren't that far off dimensionally from Intel, and that difference might shrink in the future, when the focus goes from scaling purely down to finding new materials and techniques to improve performance.

It's not that far fetched to say that Intel has never had other foundries breathing on their neck like they have right now.

Sure. It's an hard time for all foundries.

 

[cdimauro]

Uh, what mobile phone chip contracts would those be? From what I've seen over the last 10 years intel has performed dismally in mobile and the article you quoted is almost 100% counter-factual. What contracts are they even talking about? There isn't a single phone sold today by a major manufacturer that has an Intel SoC in it. In fact, there may not be any sold today period.

AFAIK x86 ZenPhones are still sold. And it's not totally excluded that Intel can go back in the mobile, in the future.

Also, if intel's density indicated a superior process then why does Apple continually chose TSMC to produce the iPhone SoC?

Because IN THE PAST Intel never opened its foundries to competitors.

But at the beginning of this year Intel exited from the mobile market, and just recently has stated that now its foundries will be opened for ARM vendors too.

Of course, this requires time for partners to evaluate Intel's productive process, and finally decide to adopt it.

If intel's process is superior, why are their own x86 chips an order of magnitude less efficient than ARM designs produced on "inferior" TSMCs process?

You're comparing apples with oranges here: they are SoCs with different components inside.

x86 chips aren't intrinsically less efficient than ARM chips. There's a nice ExtremeTech article that analyzed it.

Why is their top of the line server core showing lower IPC than Apple's mobile A10 offering?

Source for this?

What will intel do when Apple can emulate x86 instructions fast enough to remove Skylake like they did with the IBM PowerPC 750?

Ping me when it happens.

x86 isn't that easy to emulate.

Actually Apple did it before with Rosetta technology. When it will have a competitive ARM CPU even in the desktop space (and indeed if the A9/A10 is a good custom chip, it can be clocked enough), it can do like the powerPC/x86 transition. Rosetta JIT translator for old software, fat binary for new softwares. It has yet all the software infrastructure...

PowerPC is a relatively easy architecture to emulate. x86 and x64 are different beasts.