Even to paper launch at CES, AMD would have to start final production pretty soon. There wouldn't be enough time to do another spin.
It is not finished product. A0 still.
Look at an average servers clock, in the 2-3ghz range who says its less efficient?True, but we do hear that it is *process*-related.
Power efficiency and only that.
I mean AMD have more memory controllers then a E7 Xeon per socket. That's more memory bandwidth and more memory per socket. That is very important in VM farms, VM farms are massively constrained by memory throughput and total memory ( you cant over subscribe memory like you can CPU).What do you mean? It's not that easy to pack in 12 DIMMs per socket as is.
Never that simple unfortunately (layer 8/9 issues). In a standard 2P system to hit 512gb of memory E7 need's 32gb dimm's Zen can do that with 16gb Dimms. like wise 1TB, 2TB ( 64/128gb dims) at those sizes memory is the single biggest hardware cost. So it will be interesting to see how this plays out in the market. But to my clients being able to say within a 16gb or 32gb dimm size is critical to getting good value for money.Perf/cost of ownership, nothing else, last time i checked.
Luckily i can safely assume cost of purchase to be close enough and look at power efficiency ballpark for estimate. So far looks to me like Intel still has the edge here. And by no means i think it is significant in small scale. But on large enough scale? Certainly.^ and you have no info on cost of ownership of zen. and only ballpark info on performance.
Well, if we go with 8C for reference then it is 3.3Ghz all-core turbo against 3.5Ghz all-core turbo on harvested product with larger uncore. Not that great either.I see, you're complaining about the 4C part. If this is not just an ES for fun (bug hunting, sys development, testing, etc.), but will turn into a real product, then it looks to be a harvested product (there are only physical 8C dies), which exists based on its bad characteristics in the first place.
That's a valid objection, but i dare guess that it does not get much better at lower clocks.Look at an average servers clock, in the 2-3ghz range who says its less efficient?
My point here is a simple request for you to demonstrate a concept for 16 DIMMs per socket on any motherboard in existence. I want to see how cramped up it is. I'll give you that Naples should have more bandwidth.I mean AMD have more memory controllers then a E7 Xeon per socket. That's more memory bandwidth and more memory per socket. That is very important in VM farms, VM farms are massively constrained by memory throughput and total memory ( you cant over subscribe memory like you can CPU).
Once again, you are assuming that it will have 16 DIMMs per socket, not 8. Illustrate that, please.Zen can do that with 16gb Dimms.
if its process related it very well might.That's a valid objection, but i dare guess that it does not get much better at lower clocks.
Here is a 1/2 height UCS b200 blade with 24 Dimm's, I think we can fit 32Dimms in a 1 RU pizza boxMy point here is a simple request for you to demonstrate a concept for 16 DIMMs per socket on any motherboard in existence. I want to see how cramped up it is. I'll give you that Naples should have more bandwidth.
I fully expect 16dimms a socket because that's whats going to give an actual advantage, to only go 8 dimms a socket is a disadvantage.Once again, you are assuming that it will have 16 DIMMs per socket, not 8. Illustrate that, please.
P. S. Though it has to be said, a quad socket machine would do with 16gb dimms just fine.
Not sure if serious.Luckily i can safely assume cost of purchase to be close enough and look at power efficiency ballpark for estimate. So far looks to me like Intel still has the edge here. And by no means i think it is significant in small scale. But on large enough scale? Certainly.
Well, if we go with 8C for reference then it is 3.3Ghz all-core turbo against 3.5Ghz all-core turbo on harvested product with larger uncore. Not that great either.
edit: here is a nice 4P board with 48 DIMM's, so plently of room for 2P with 32
http://www.intel.de/content/dam/www...server-board-s4600lh-s4600lt-back-view-lg.jpg
3150MHZ based fits my expectation.
Yeah, Broadwell-EP supports 3 DIMMs per channel. You take a performance hit if you use three though so I bet it's rare in actual usage. I'm guessing the slots that are blue are the slow ones.
I suppose it is possible that they found no issues with A0, that would be pretty rare, but not unheard of.It is not finished product. A0 still.
This is same stepping as the Hot chips presentation... If they stick to feb 17 volume, i think that at least two other steps are produced... I think that a new step is already in the labs...I suppose it is possible that they found no issues with A0, that would be pretty rare, but not unheard of.
Normally, it was said that you need 45-60 days between steppings, so if A0 is final silicon they could make that Feb deadline that was mentioned. If not, then looks like this could get pushed to into May/June.
For all we know, they might even have a Samsung made chip up and running as well that is a later revision.
Once again, check actual power consumption instead of TDP bracket. Intel could really label 6900k as 95W TDP chip if they wanted to be as misleading as AMD sometimes areNot sure if serious.
"3.3Ghz all-core turbo @95w against 3.5Ghz all-core turbo @140w"
tell me who has the edge here ? or you will back-paddle to "oh we don't have enough info on this and that". as i said nobody knows cost of ownership of zen.
i'm not saying it will be better but not dismissing the possibility of it either.
Well, that's the thing. Your own pictures have DIMMs + 2 narrow sockets take up entire board width. 16 DIMMS and what is most likely a larger socket (i mean, 8 channels, come on) just means it would take a really funky DIMM layout to fit in.I fully expect 16dimms a socket because that's whats going to give an actual advantage, to only go 8 dimms a socket is a disadvantage.
Well, that's the thing. Your own pictures have DIMMs + 2 narrow sockets take up entire board width. 16 DIMMS and what is most likely a larger socket (i mean, 8 channels, come on) just means it would take a really funky DIMM layout to fit in.
Once again, check actual power consumption instead of TDP bracket. Intel could really label 6900k as 95W TDP chip if they wanted to be as misleading as AMD sometimes are
Look: plain 6700 has 4Ghz single core boost, 3.6Ghz all core boost and 3.4Ghz base clock and iGPU @ 65W. Compared to 3.1Ghz all core turbo, 3.4Ghz single core turbo without iGPU in 65W. Uncore is fairly similar as well.
Exactly. so why you were doing this -
which actually consumes pretty much same and more than 85w as 6700k does. which is rated @91w.
Exactly. so why you were doing this -
which actually consumes pretty much same and more than 85w as 6700k does. which is rated @91w.
funny you did exactly what you tell others not to do.
Exactly. so why you were doing this -
which actually consumes pretty much same and more than 85w as 6700k does. which is rated @91w.
funny you did exactly what you tell others not to do.
Tools are getting better, as do FPGAs, etc.As discussed before, I'd be very surprised if A0 was final silicon...
I would still be very surprised, from a totally new uarch and process standpoint. I'd suspect the pushout from Q4 to Q1 was for clocks@power rather than anything else.Tools are getting better, as do FPGAs, etc.
This likely is also mask cost driven.
Once again, check actual power consumption instead of TDP bracket. Intel could really label 6900k as 95W TDP chip if they wanted to be as misleading as AMD sometimes are
I would still be very surprised, from a totally new uarch and process standpoint. I'd suspect the pushout from Q4 to Q1 was for clocks@power rather than anything else.
It is not finished product. A0 still.
Only on that particular blade enclosure, in pizza boxes your fine and a blade chassis with an extra RU of height your fine. I fully expect intel in the future to add more memory channels as well as they continue to increase cores per socket.