New Zen microarchitecture details

[lolfail9001]

Even with the Polaris 11 GPU a Quad Core RavenRidge APU will be sub 200mm2.

Actually, with Polaris 11 GPU, RR APU would be over 200mm^2 with ease. You are replacing a CCX (44mm^2 or something) with P11 (123mm^2). Basically it would be like 260-270mm^2, if 180-190 estimation is on point.

 

[Glo.]

Nice,

Even with the Polaris 11 GPU a Quad Core RavenRidge APU will be sub 200mm2.

You didn't accounted that 1024 GCN core Vega, made from two 8 CU Shader Engines will be slightly bigger than Polaris 11. So it will deffinitely be bigger in die size than 200 mm2. Bigger, but not bigger than Polaris 10. So the end-user prices can range from 170 to 350$, and AMD still will make profit on this die.

 

[CatMerc]

Actually, with Polaris 11 GPU, RR APU would be over 200mm^2 with ease. You are replacing a CCX (44mm^2 or something) with P11 (123mm^2). Basically it would be like 260-270mm^2, if 180-190 estimation is on point.

There would be a lot of variables at play here. For example inter-CCX communication wouldn't need to be present, nor would the links required for the Naples MCM packaging. And the GPU on Raven wouldn't have its 128bit GDDR5 controller, rather a 64bit DDR4 controller (To combine with the controller on the CCX to create a dual channel system).

I'm not agreeing or disagreeing, just saying that it's not that simple.

 

[Glo.]

https://www.techpowerup.com/230464/...urfaces-mark-your-calendars-for-february-28th

4.2 GHz?

 

[Veradun]

https://www.techpowerup.com/230464/...urfaces-mark-your-calendars-for-february-28th

4.2 GHz?

TurboF, maybe?

 

[Glo.]

More importantly: what core count is that CPU. 4C/8T? Or 6C/12T? 4C/8T at 299$ is meh, even with 4.2 GHz core clock. 6C/12T at 4.2 GHz, and 299$ is amazing deal.

 

[Abwx]

Canard PC just stated that all cores boost is to be set between 3.65 and 3.8GHz depending on yields.

This give weight to BJT2 statement that they could hit as high as 4GHz@95W with all cores, if not at launch this should require only a slight maturation of the specific productions lines at GF.

https://www.cpchardware.com/ryzen-les-frequences-a-la-loupe/

 

[Doom2pro]

If AMD Zen based APUs use the MCM technique, it doesn't matter how big Zen is or how big the iGPU is... They will be individual dies fabbed on separate wafers with their own respective yields.

All AMD has to do is bin them and then glue them together on an organic package with Infinity Fabric. This would be killer for AMD as in the past they have had to merge CPU and GPU designs and libraries and then compromise on a single library density for both on a single mask set and then reap the yields from the resulting large die.

Now they can use separate library densities and mask sets for each respective CPU and GPU without having to compromise on library densities, and reaping the benefits of yields from two separate designs and then link them together in an MCM with Infinity Fabric.

Tada, Zen based APU with Vega Graphics in an MCM with separate dies and no need to scavenge dies with defective iGPUs.

 

[CatMerc]

So I uh, got bored and had nothing better to do... So...

I present - FrankenDie:

Spoiler: IT'S ALIVE

11 CU's
16 ROP's
I stretched and squashed various parts, but I made sure they always take the same area, and I didn't overdo it by turning a block into a long string that goes around the die or anything like that lol.

Edit: Realized that 16 ROPs would probably be overkill for 11 CU's, so here's the 8 ROPs variant:

Spoiler: Still Alive

 

[Doom2pro]

So I uh, got bored and had nothing better to do... So...

I present - FrankenDie:

11 CU's
16 ROP's
I stretched and squashed various parts, but I made sure they always take the same area, and I didn't overdo it by turning a block into a long string that goes around the die or anything like that lol.

Since you have the free time, now make an MCM package with a 4c/8t Zen SOC die + a Vega GPU die on separate dies connected via Infinity Fabric.

And if AMD doesn't have a 4c/8t design and only uses 8c/16t designs for 4c SKUs use a salvaged 8c/16t die and a Vega die on an MCM...

Now die size and yields don't matter so much.

 

[Glo.]

I have been digging, and came to conclusion, that if Raven Ridge APU will have HBM2, and it will be available to both: CPU and GPU, that means we are looking not at 4C/8T + 16 CU MCM package, one, separate design.

HBM2 memory controller must be on the die, to get it functional for both: CPU and GPU. Overall die size should not be bigger than 220mm2 for 4C/8T + 16 CU design.

Ryzen CPU is 180-190 mm2. So there is some of room to play with for "Frankensteining" the Raven Ridge APU from Ryzen + Polaris dies .

 

[TemjinGold]

https://www.techpowerup.com/230464/...urfaces-mark-your-calendars-for-february-28th

4.2 GHz?

4.2 ghz base cock?

 

[Arachnotronic]

If AMD Zen based APUs use the MCM technique, it doesn't matter how big Zen is or how big the iGPU is... They will be individual dies fabbed on separate wafers with their own respective yields.

APUs won't be MCM, they'll be integrated. On-die integration is always better for performance than MCM.

 

[Doom2pro]

APUs won't be MCM, they'll be integrated. On-die integration is always better for performance than MCM.

That is assuming the older on-die integration performance is significantly better than what Infinity Fabric can offer and since we don't know the latter, we can't assume the former.

I would not be surprised if Infinity Fabric is the glue that connects Zen and Vega into an APU, after all AMD has been hyping IF hard core like it's the second coming of Hyper Transport.

Do you really doubt their inter module communication IP considering they practically invented HBM and Hypertransport?

 

[CentroX]

That ryzen product is probaby placeholder.

 

[raghu78]

That is assuming the older on-die integration performance is significantly better than what Infinity Fabric can offer and since we don't know the latter, we can't assume the former.

I would not be surprised if Infinity Fabric is the glue that connects Zen and Vega into an APU, after all AMD has been hyping IF hard core like it's the second coming of Hyper Transport.

Do you really doubt their inter module communication IP considering they practically invented HBM and Hypertransport?

Infinity fabric is the key technology which powers everything AMD is building going forward. IF will be present in every AMD product going forward - CPUs, GPUs and APUs. imo IF might be the most important AMD innovation since the original Athlon 64 and Hypertransport. IF brings a level of granularity and scalability unseen before. IF will scale from on die to on package to across sockets, across PCI-E links and maybe even more . AMD has not yet revealed all the details but IF is a huge deal.

http://semiaccurate.com/2017/01/19/amd-infinity-fabric-underpins-everything-will-make/

 

[krumme]

IF looks like Jim Keller most important work to me. And i asume he is the co author of this as he was on hypertransport.

If amd opens up for others it will be one of the most important concepts ever for microprocessers as it enable a new way computing is done.

Most noteworthy is imo the separation of control/safety (latency) and data (bandwith). Makes it far more flexible.

I think hypertransport pales in comparison to it. Its the kind of modular platform thinking that the car industry have been exploiting and refining for decades. We need more of that.

 

[scannall]

Mark Papermaster was very clear about no HBM2 in 2017. The cost wasn't there yet. Unfortunate. 2018? Possible. 2019? Probable.

Perhaps someone more learned than I can answer this though. When HBM2 is cost effective, is there any particular reason AMD couldn't use separate dies for the CPU and GPU in an APU? With the HBM2 feeding just the GPU portion, and the CPU going out to DDR4? With the infinity mesh wrapping it up with a bow on top?

 

[raghu78]

Canard PC just stated that all cores boost is to be set between 3.65 and 3.8GHz depending on yields.

This give weight to BJT2 statement that they could hit as high as 4GHz@95W with all cores, if not at launch this should require only a slight maturation of the specific productions lines at GF.

https://www.cpchardware.com/ryzen-les-frequences-a-la-loupe/

I can definitely foresee a 3.8 Ghz 8C/16T with 4 Ghz Turbo right in time for Skylake-X. Process maturity, production ramp yield learning and maybe a stepping if needed. Voila you have it ready.

Mark Papermaster was very clear about no HBM2 in 2017. The cost wasn't there yet. Unfortunate. 2018? Possible. 2019? Probable.

Perhaps someone more learned than I can answer this though. When HBM2 is cost effective, is there any particular reason AMD couldn't use separate dies for the CPU and GPU in an APU? With the HBM2 feeding just GPU portion, and the CPU going out to DDR4? With the infinity mesh wrapping it up with a bow on top?

HBM2 will be used as a common L4 cache as AMD APUs support a single address space. CPU and GPU can share pointers. This is only possible with a design where HBM2 is a high bandwidth cache. AMD Vega's High bandwidth cache controller is a dead giveaway that this is the design of the future.

 

[BeepBeep2]

HBM2 will be used as a common L4 cache as AMD APUs support a single address space. CPU and GPU can share pointers. This is only possible with a design where HBM2 is a high bandwidth cache. AMD Vega's High bandwidth cache controller is a dead giveaway that this is the design of the future.

I was thinking eSRAM / eDRAM?

 

[raghu78]

I was thinking eSRAM / eDRAM?

Both these are not options due to the capacity and die size/cost constraints. HBM2 is the best option as you get massive bandwidth which GPUs need at low power and they can be manufactured on cheaper DRAM processes.

 

[BeepBeep2]

Both these are not options due to the capacity and die size/cost constraints. HBM2 is the best option as you get massive bandwidth which GPUs need at low power and they can be manufactured on cheaper DRAM processes.

Xbox One - 32MB eSRAM GPU cache (218 GB/s)
Broadwell Iris Pro 6200/P6300 - 128MB eDRAM shared L4

Not saying I would be betting money on it happening but I felt it could be a possibility. Raven Ridge is not going to have HBM2 and though there is easy space for 16 CUs it is still going to be bandwidth choked if it has only 8.

Having a memory controller design that can work with a large cache could probably use 256MB eDRAM effectively?

 

[NostaSeronx]

Raven Ridge is not going to have HBM2 and though there is easy space for 16 CUs it is still going to be bandwidth choked if it has only 8.

Shhh.. no one needs to know.
https://www.rambus.com/memory-and-interfaces/ddrn-phys/hbm/

• East-West orientation (PHY can be placed in corner of die)

http://i.imgur.com/OOHK1bH.jpg
I circled the HBM2 phys for you. It is part of the CCX. ;P
(Check Fiji's HBM Phys then compare and correlate to those.. hint: they match.)

With the addition of Vega and Infinity Fabric and High Bandwidth Cache Controllers in the L3(CCX) & Uncore(Vega) => HBM is assured.

16 CUs are not needed because Vega CUs have the ability to shoot 128 32-bit ops compared to Polaris->Southern Islands 64 32-bit ops. With that and plus Vega CUs can split into smaller SIMDs as well to increase utilization absolute destroying previous generations. Hence, why Raven Ridge is mostly 12 CUs aka 1536 32-bit ops.

 

[lopri]

This is only tangentially related to the earlier disclosed die sizes of AMD and Intel's 14nm cores.

v. mobile SOCs

But still interesting. ^^

 

[AtenRa]

Actually, with Polaris 11 GPU, RR APU would be over 200mm^2 with ease. You are replacing a CCX (44mm^2 or something) with P11 (123mm^2). Basically it would be like 260-270mm^2, if 180-190 estimation is on point.

1. RavenRidge APU doenst need all the IC that SummitRidge has for Servers. Quad Core + PCH + 128bit DDR-4 should be not more than 100mm2
2. You have to take-off Polaris 128bit GDDR-5 memory controllers (16-20mm2), you only need the DDR-4 on the CPU. So the die comes down to ~100mm2

1+2 = max 200mm2