Next gen Zen 2/3 "Starship" and derivatives

[Blitzvogel]

I'm just talking abut the iGPU using on package memory. Like Intel did with Iris Pro.

Crystalwell forced all such equipped processors to be BGA, making drop in upgrades a no-no, and the subsequent availability very limited. Not to mention it was expensive. Kabylake-G as it's successor is reflected in the same kind of premium pricing.

Anyways, BGA is not a problem for mobile. However, the desktop market expects upgradeability and flexibility of choice in AM4 motherboard, so a big HBM equipped APU would need to be socketed. Space is already a premium on the AM4 package, and currently Raven Ridge isn't powerful enough to really make HBM worth it. I believe HBM could fit if the APU die was shifted up or down, and the on package capacitors were moved accordingly. But the bigger you make the APU, the less space there is on the AM4 socket package for the HBM. The other way around this problem is HBM stacked on the APU die, but AMD isn't ready for this yet.

The more TFLOPS you can deliver, the more price you can command out of the product, and in the process sort of subsidize the cost of the HBM and socket packaging with interposer built in. 1.7 TFLOPS for the 2400G doesn't warrant that kind of price hike unless you go with 2GB of HBM (which would still be at least $30 over the 2400G), and now you're just stuck in between the RX 550 and RX 560 which isn't all that impressive for dedicated graphics. This is in consideration of the RX 560 being a ~$100 product before the GPU-ocalypse. Not to mention now you have a single premium product and specialty package that uses it. RR needs more compute units for more TFLOPS and inevitable binned versions.

Using the minimum SKU for Kabylake-G as an example for minimum TFLOPS to make HBM worth it (RX Vega M GL), we need about 2.6 TFLOPS of graphics performance, at minimum, and KB-G is a $500 product. Raven Ridge as we know it is 210mm². Adding the HBM memory controllers and increasing the compute units to the same 1280 SPs as RV Vega M GL would take the APU close to 300mm², really constraining the room on the AM4 package, if not making room for the HBM impossible. At 1300 MHz, this version would give us 3.3 TeraFLOPS of graphics compute, and the subsequent overhead for at least 2 binned versions.

But realistically, the bigger the APU, the more powerful it is (obviously) and the more suited the expensive HBM is going to be. It's just a matter of if the socket can be ditched in the long run. And a switch to the TR4 socket would just be undermining the more value oriented proposition of APUs because of the platform expense.

 

[CatMerc]

The highest overclock on air is at 5.7GHz. Above that, you need exotic cooling solutions, and the majority end up at 5.5GHz or less on air. That's usually using tricks as well. Like having only 1 core active, or Hyperthreading off, or running only the monitoring application.

The highest overclock ever was achieved by AMD FX and is at 8.79GHz frequency. Remember FX chips are based on the architecture with very long pipelines. Prescott Celeron chips are also among the top max overclock chips.

Interestingly, Sandy Bridge still seems to be the top core for highest air overclock. While Sandy Bridge can do it with 4 cores active, the similar clocks achieved by Broadwell-E is only done with 1 core.

Again, those are not stable overclocks. Stable overclocks end up at 5.2GHz or so. The amount of effort required above that point seems to indicate a physics limit, because it applies across ISAs, fabs, uarchs, and different process/lithography.

IBM's ZEC12 is the highest clocked commercial chip at 5.5GHz, but requires 300W to do so. Certain configurations on that server calls for liquid cooling, and IBM has very impressive packaging technologies for their POWER line, so for average folks, it may be just as exotic as using LN2. Intel chips like Kabylake and Coffeelake merely reduces the gap between max OC clock and stock clocks.

In short: 6GHz was never doable.

FX chips don't actually have a very long pipeline. It's in the lower 20's, while Zen is 19.
https://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2

With 7nm HPC 6GHz on air might be doable if you pull every trick (single core, no SMT, etc')

 

[CatMerc]

Did my own calibration:

Based the 4GHz and 3.7GHz numbers based on bit-tech and tomshardware power consumption results, respectively.

 

[raghu78]

There is a lot more to achieving high clock speed than process alone.

Remember when AMD said they threw something like a Billion extra transistor at Vega to get clock speed up?

I seriously doubt we will see 5+GHz Ryzens on 7nm. That seems more like wishful thinking at this point.

Zen is a high frequency design currently limited by process alone. We will see 12LP push Zen+ firmly into 4.6+ Ghz range. Gary Patton has said in his interview with anandtech that he expects 7HPC to drive clocks in the 5 Ghz range. I think we will see max turbo clocks of 5 Ghz with Ryzen 2.

https://www.anandtech.com/show/1243...ew-with-dr-gary-patton-cto-of-globalfoundries

Q17: Does the first generation of 7LP target higher frequency clocks than 14LPP?

GP: Definitely. It is a big performance boost - we quoted around 40%. I don't know how that exactly will translate into frequency, but I would guess that it should be able to get up in the 5GHz range, I would expect.

We will see eventually.

Getting clock-speed up on tighter packed transistors tends to create issues, you end up with a lot more heat/area on the smaller die creating cooling issues, and it looks like Intel made some features larger on 14nm++ to improve higher clock speeds.

My bet is 7nm SoC will likely be less problematic in practice than 7nm HPC. I wouldn't be surprised if HPC ends up delayed.

There are 2 libraries at 7LP

1. High density 7SoC 6T . H240 cell . 2 fin cell. 13 Metal layers
2. High performance 7HPC 9T. H360 cell . 4 fin cell. 17 Metal layers

GF has designed 7HPC specifically for AMD and IBM 's high performance CPU requirements. I expect Ryzen 3000 will be built using 7HPC while 7nm Rome (EPYC successor) will be built using 7SoC. AMD has moved to a purpose built die for Zen+ at 12LP built with high performance libraries . Tom Caulfield, General Manager Fab 8 confirmed AMD is going with relaxed CPP= 84nm for maximum performance . I think we will see Zen+ go with 10.5T cell height . 12LP with MMP = 56nm , CPP=84nm and 10.5T will have a cell area 10% larger than 14LPP High density libraries (MMP=64nm CPP=78nm 9T) but since Pinnacle Ridge is a client only die the I/O options will be trimmed wrt the Zeppelin die which was used in server and client. I think we will see a 5% die size increase and a die size around 230 sq mm. But we will see clocks go up in a big way.

Gary Patton also stated at 7LP+ they will do something similar to 12LP (see question 11). I expect a relaxed CPP of 64nm but with a tigher M0 metal layer of 36nm which is the 2D EUV limit.

"The 2nd phase would be leveraging it to really get a shrink using EUV. We will apply it selectively, kind of like we're doing with 12."

 

[raghu78]

FX chips don't actually have a very long pipeline. It's in the lower 20's, while Zen is 19.
https://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2

With 7nm HPC 6GHz on air might be doable if you pull every trick (single core, no SMT, etc')

6 Ghz is not happening on air or water. The best case for 7LP would be 5.5 Ghz With 7LP+ maybe they could push it a bit closer to 6 Ghz on custom water cooling maybe.

 

[CatMerc]

Zen is a high frequency design currently limited by process alone. We will see 12LP push Zen+ firmly into 4.6+ Ghz range. Gary Patton has said in his interview with anandtech that he expects 7HPC to drive clocks in the 5 Ghz range. I think we will see max turbo clocks of 5 Ghz with Ryzen 2.

https://www.anandtech.com/show/1243...ew-with-dr-gary-patton-cto-of-globalfoundries

Q17: Does the first generation of 7LP target higher frequency clocks than 14LPP?

GP: Definitely. It is a big performance boost - we quoted around 40%. I don't know how that exactly will translate into frequency, but I would guess that it should be able to get up in the 5GHz range, I would expect.

There are 2 libraries at 7LP

1. High density 7SoC 6T . H240 cell . 2 fin cell. 13 Metal layers
2. High performance 7HPC 9T. H360 cell . 4 fin cell. 17 Metal layers

GF has designed 7HPC specifically for AMD and IBM 's high performance CPU requirements. I expect Ryzen 3000 will be built using 7HPC while 7nm Rome (EPYC successor) will be built using 7SoC. AMD has moved to a purpose built die for Zen+ at 12LP built with high performance libraries . Tom Caulfield, General Manager Fab 8 confirmed AMD is going with relaxed CPP= 84nm for maximum performance . I think we will see Zen+ go with 10.5T cell height . 12LP with MMP = 56nm , CPP=84nm and 10.5T will have a cell area 10% larger than 14LPP High density libraries (MMP=64nm CPP=78nm 9T) but since Pinnacle Ridge is a client only die the I/O options will be trimmed wrt the Zeppelin die which was used in server and client. I think we will see a 5% die size increase and a die size around 230 sq mm. But we will see clocks go up in a big way.

Gary Patton also stated at 7LP+ they will do something similar to 12LP (see question 11). I expect a relaxed CPP of 64nm but with a tigher M0 metal layer of 36nm which is the 2D EUV limit.

"The 2nd phase would be leveraging it to really get a shrink using EUV. We will apply it selectively, kind of like we're doing with 12."

Where did Tom confirm a relaxed CPP for AMD?

 

[raghu78]

Where did Tom confirm a relaxed CPP for AMD?

http://www.thetechanalysts.com/home/2018/02/ep10-2518-building-a-true-global-foundry

About 12LP at 12:30 - 14:30

The competition at 16nm is TSMC with CPP=90nm . AMD used GF 14LPP High density CPP = 78nm for Zen. For Zen+ they are going with performance option. CPP=84nm

 

[PeterScott]

http://www.thetechanalysts.com/home/2018/02/ep10-2518-building-a-true-global-foundry

About 12LP at 12:30 - 14:30

The competition at 16nm is TSMC with CPP=90nm . AMD used GF 14LPP High density CPP = 78nm for Zen. For Zen+ they are going with performance option. CPP=84nm

Sounds like AMD didn't want to do a new tapeout for 12nm, so size will remain the same and they get some performance improvements.

Later it also sounds like he is saying 7nm won't production ramp till 2020.

 

[CatMerc]

http://www.thetechanalysts.com/home/2018/02/ep10-2518-building-a-true-global-foundry

About 12LP at 12:30 - 14:30

The competition at 16nm is TSMC with CPP=90nm . AMD used GF 14LPP High density CPP = 78nm for Zen. For Zen+ they are going with performance option. CPP=84nm

All I've heard here is that AMD keeping the density the same for the sake of performance. I didn't hear anything that would imply they're going with looser pitches.

 

[raghu78]

All I've heard here is that AMD keeping the density the same for the sake of performance. I didn't hear anything that would imply they're going with looser pitches.

Relaxed CPP=84nm and Taller track library (10.5T) are few of the Performance elements which Tom talks about along with the transistor level improvements in 12LP. 14LPP also had relaxed CPP library options High performance (9T CPP=84nm) and Ultra High performance (10.5T CPP=84nm). But AMD used 14LPP High density (9T CPP=78nm) for Zeppelin and optimized for maximum logic density and low power as it was a server optimized design.

https://pc.watch.impress.co.jp/docs/column/kaigai/733713.html
https://pc.watch.impress.co.jp/img/pcw/docs/733/713/html/12.jpg.html
https://pc.watch.impress.co.jp/img/pcw/docs/733/713/html/9.jpg.html

 

[NostaSeronx]

AMD is most likely keeping the 78CPP/64Mx for Zeppelin on 12nm LP. It provides the fastest and cheapest port to market.

The best design is to follow Qualcomm in mixed standard cell heights for logic. Get the best 7.5T, 9T and 10.5T, would fall under the same optimizations as LVT, RVT, HVT selections.

Area vs Freq
https://i.imgur.com/wzwYv9W.png

Power vs Freq
https://i.imgur.com/1CPFNj9.png

3-track selection Area vs Freq
https://i.imgur.com/XNfAZwY.png

3-track selection Power vs Freq
https://i.imgur.com/2Kop9vf.png

The above was done in a unspecified 28nm LP node. There is a lot more selection to be had than what Qualcomm had for those nodes;
http://www.dolphin-ic.com/global_28slp_cell.html
http://www.dolphin-ic.com/tsmc_28lp_cell.html

Take the above and apply it to 7LP with both HPC and SoC packages. Win, win.

// Mixed designs have been used before: https://hothardware.com/gallery/Article/2588?image=big_ryzen-l2.jpg&tag=&p=1
6T SRAM and 8T SRAM, etc. So, all AMD needs to do is extend that to logic cells.

 

[CatMerc]

AMD is most likely keeping the 78CPP/64Mx for Zeppelin on 12nm LP. It provides the fastest and cheapest port to market.

The best design is to follow Qualcomm in mixed standard cell heights for logic. Get the best 7.5T, 9T and 10.5T, would fall under the same optimizations as LVT, RVT, HVT selections.

Area vs Freq
https://i.imgur.com/wzwYv9W.png

Power vs Freq
https://i.imgur.com/1CPFNj9.png

3-track selection Area vs Freq
https://i.imgur.com/XNfAZwY.png

3-track selection Power vs Freq
https://i.imgur.com/2Kop9vf.png

The above was done in a unspecified 28nm LP node. There is a lot more selection to be had than what Qualcomm had for those nodes;
http://www.dolphin-ic.com/global_28slp_cell.html
http://www.dolphin-ic.com/tsmc_28lp_cell.html

Take the above and apply it to 7LP with both HPC and SoC packages. Win, win.

// Mixed designs have been used before: https://hothardware.com/gallery/Article/2588?image=big_ryzen-l2.jpg&tag=&p=1
6T SRAM and 8T SRAM, etc. So, all AMD needs to do is extend that to logic cells.

Seems like a fairly obvious solution. Any reason why it's not always used?

 

[raghu78]

AMD is most likely keeping the 78CPP/64Mx for Zeppelin on 12nm LP. It provides the fastest and cheapest port to market.

12LP is a partial optical shrink , MOL and BEOL specifically as confirmed by Gary Patton. Gary also has given hints that 12FDX and 12LP share same MMP of 56nm. See question 6 , 7 and 30 of anandtech inteview

https://www.anandtech.com/show/1243...ew-with-dr-gary-patton-cto-of-globalfoundries

https://www.eetimes.com/document.asp?doc_id=1332328
https://m.eet.com/content/images/eetimes/1 7 12 14 copared x 800_1505972923.jpg

My guess as to what libraries PR is built 12LP MMP=56nm CPP=84nm and 10.5T
12LP cell area = 56 x 84 x 10.5 = 49392
14LLP cell area = 64 x 78 x 9 = 44928

Roughly 10% larger cell area. But PR is a client only die and some of the extensive server I/O options from Zeppelin can be removed in PR die. I think a 230 sq mm PR die can be built with Ultra high performance libraries.

 

[PeterScott]

Relaxed CPP=84nm and Taller track library (10.5T) are few of the Performance elements which Tom talks about along with the transistor level improvements in 12LP. 14LPP also had relaxed CPP library options High performance (9T CPP=84nm) and Ultra High performance (10.5T CPP=84nm). But AMD used 14LPP High density (9T CPP=78nm) for Zeppelin and optimized for maximum logic density and low power as it was a server optimized design.

https://pc.watch.impress.co.jp/docs/column/kaigai/733713.html
https://pc.watch.impress.co.jp/img/pcw/docs/733/713/html/12.jpg.html
https://pc.watch.impress.co.jp/img/pcw/docs/733/713/html/9.jpg.html

From the audio link you included before, they aren't talking about relaxing anything, they are talking about AMD reusing the same design, so they don't get a shrink. It sounds like AMD is skipping doing a full new tapeout, so they don't get a shrink.

Begin Transcription:

We're on to 12nm here, ... How's that going:

We've recently announced, in fact so did AMD, that they're going to leverage our next increment on our 14nm LPP, to do something called 12nm LPP, ...

13:13 - How we've allowed our customers to leverage it is, hey, if you already have a design, and you don't want to take advantage of some of the denser tech track libraries, and get the shrink part of that offering, well since we already started at 14 and the competition was 16, maybe you don't need as much shrink, but all the performance elements that come along, you can put that into the design.

13:35 - Or, if you are starting with a new design, take advantage of the libraries of that allow for that shrink in the design, to get more die per wafer, therefore lower cost/die, and also take advantage of the performance.

13:51 - Well, we have customer have done just that, some have just recently taped out, taking advantage of the shrink and performance, we have some of AMD's products, were they're just hey, "I got a great design, I'm just going to take advantage of the performance, and future designs will take that...

14:33 On 7nm: ( highlights as I am tired of transcribing).
We're a fast follower on that, first tapeout later this year, ... never goes to market ... eventually goes to production ramp, 2nd half of 2020.

 

[raghu78]

As much as I would love to see that, even AMD's own figures for the performance improvement aren't quite near that (a 10% improvement was mentioned by multiple, reliable sources IIRC). They could be rather conservative and probably are, but I'm expecting a 15% improvement in general, significantly better in some cases but worse in others. Still, I hope that your prediction about the 12LP process they will be using are correct.

From the audio link you included before, they aren't talking about relaxing anything, they are talking about AMD reusing the same design, so they don't get a shrink. It sounds like AMD is skipping doing a full new tapeout, so they don't get a shrink.

Begin Transcription:

We're on to 12nm here, ... How's that going:

We've recently announced, in fact so did AMD, that they're going to leverage our next increment on our 14nm LPP, to do something called 12nm LPP, ...

13:13 - How we've allowed our customers to leverage it is, hey, if you already have a design, and you don't want to take advantage of some of the denser tech track libraries, and get the shrink part of that offering, well since we already started at 14 and the competition was 16, maybe you don't need as much shrink, but all the performance elements that come along, you can put that into the design.

13:35 - Or, if you are starting with a new design, take advantage of the libraries of that allow for that shrink in the design, to get more die per wafer, therefore lower cost/die, and also take advantage of the performance.

13:51 - Well, we have customer have done just that, some have just recently taped out, taking advantage of the shrink and performance, we have some of AMD's products, were they're just hey, "I got a great design, I'm just going to take advantage of the performance, and future designs will take that...

14:33 On 7nm: ( highlights as I am tired of transcribing).
We're a fast follower on that, first tapeout later this year, ... never goes to market ... eventually goes to production ramp, 2nd half of 2020.

"well since we already started at 14 and the competition was 16, maybe you don't need as much shrink, but all the performance elements that come along, you can put that into the design."

The performance elements are what negate the shrink to 12LP. GF offers performance option CPP = 84nm with all of its libraries (7.5T,9T,10.5T) at 12LP. I got this confirmed from GF by Daniel Nenni of semiwiki.

TSMC 16FF+ - CPP = 90nm MMP=64nm 9T Cell Area = 90 x 64 x 9 = 51840 sq nm
GF 14LPP High density CPP=78nm MMP=64nm 9T Cell Area = 78 x 64 x 9 = 44928 sq nm

So if you optimize for high density using 12LP 7.5T and CPP=78nm you get a significant shrink
12LP High density CPP=78nm MMP=56nm 7.5T Cell Area = 78 x 56 x 7.5 = 32760

If you optimize for high performance using 12LP 9T and CPP=84nm you still get a mild shrink vs 14LPP High density 9T CPP=78nm
12LP High Performance CPP=84nm MMP=56nm 9T Cell Area = 84 x 56 x 9 = 42336

If you go for max performance with 12LP 10.5T and CPP=84nm
12LP Ultra High Performance CPP=84nm MMP=56nm 10.5T Cell Area = 84 x 56 x 10.5 = 84 x 56 x 10.5 = 49392

My guess is PR uses the max performance on 12LP. around 10% larger cell area vs 14LPP High density. But with PR being a client only die the extensive server I/O options in Zeppelin can be reduced for desktop use case. The nett die size increase on PR could ed up being 5% for a massive boost in clocks which is what I expect it to deliver.

 

[jpiniero]

My guess is PR uses the max performance on 12LP. around 10% larger cell area vs 14LPP High density. But with PR being a client only die the extensive server I/O options in Zeppelin can be reduced for desktop use case. The nett die size increase on PR could ed up being 5% for a massive boost in clocks which is what I expect it to deliver.

They aren't doing this. They need a backup plan for Epyc in case GloFo doesn't deliver with 7 nm, and you will see Threadripper parts at some point too.

 

[raghu78]

They aren't doing this. They need a backup plan for Epyc in case GloFo doesn't deliver with 7 nm, and you will see Threadripper parts at some point too.

There is no EPYC refresh on 12LP. AMD is going directly to 7nm Rome. Gary Patton has said 7LP is on track for risk production by mid-2018 and volume production by early 2019. You can expect to see 7nm Rome launch by Q2 2019.

https://www.fudzilla.com/news/processors/43682-data-center-7nm-is-rome

https://www.anandtech.com/show/1243...ew-with-dr-gary-patton-cto-of-globalfoundries

Q15: With the first generation of 7nm, do you expect to be high volume production by the end of the year?

GP: By the end of the year or most likely in early 2019, with a couple of key partners. Our ASIC customers, of which there are quite a few, are also lead users of our 7nm process.

I think we will see 7nm Rome tapeout this quarter if it has not already been.

 

[PeterScott]

"well since we already started at 14 and the competition was 16, maybe you don't need as much shrink, but all the performance elements that come along, you can put that into the design."

The performance elements are what negate the shrink to 12LP. GF offers performance option CPP = 84nm with all of its libraries (7.5T,9T,10.5T) at 12LP. I got this confirmed from GF by Daniel Nenni of semiwiki.

No, design reuse is what negates the shrink. He clearly states that you can do a new design and get both a performance improvement, and a die shrink, or you can reuse an old design an ONLY get the performance improvements.

13:35 - Or, if you are starting with a new design, take advantage of the libraries of that allow for that shrink in the design, to get more die per wafer, therefore lower cost/die, and also take advantage of the performance.

 

[CatMerc]

No, design reuse is what negates the shrink. He clearly states that you can do a new design and get both a performance improvement, and a die shrink, or you can reuse an old design an ONLY get the performance improvements.

13:35 - Or, if you are starting with a new design, take advantage of the libraries of that allow for that shrink in the design, to get more die per wafer, therefore lower cost/die, and also take advantage of the performance.

You get the partial performance improvement when doing a redesign for higher density. You can get a bigger performance uplift if you maintain the density.

12nm LP is 10% higher clockspeed at ISO power when comparing 7.5T to 9T on 14LPP. If you keep 12nm LP on 9T, then you get a bigger uplift.

 

[Hitman928]

// Mixed designs have been used before: https://hothardware.com/gallery/Article/2588?image=big_ryzen-l2.jpg&tag=&p=1
6T SRAM and 8T SRAM, etc. So, all AMD needs to do is extend that to logic cells.

6T and 8T SRAM cells refer to how many transistors are used to make up the cell (6 transistor, 8 transistor), this is very different than mixing different track levels between logic cells which would be much more difficult to do in a modern CPU.

 

[raghu78]

No, design reuse is what negates the shrink. He clearly states that you can do a new design and get both a performance improvement, and a die shrink, or you can reuse an old design an ONLY get the performance improvements.

13:35 - Or, if you are starting with a new design, take advantage of the libraries of that allow for that shrink in the design, to get more die per wafer, therefore lower cost/die, and also take advantage of the performance.

Firstly even to move an existing 14LPP design to a 12LP design involves a recompiling as there is MMP shrink from 64nm to 56nm. Gary Patton has confimed a partial optical shrink, MOL and BEOL specifically. So the remaining choices are whether you are targetting density or maximum performane. For maximum density you go for 7.5T with CPP=78nm and for performance you choose the combination of track height and relaxed CPP to fit your product goals. My prediction is AMD has a design which needs max performance and they are not interested in the shrink but in the performance improvements with 12LP. Anyway I stand strongly by my predictions so lets see how PR turns out.

 

[CatMerc]

Firstly even to move an existing 14LPP design to a 12LP design involves a recompiling as there is MMP shrink from 64nm to 56nm. Gary Patton has confimed a partial optical shrink, MOL and BEOL specifically. So the remaining choices are whether you are targetting density or maximum performane. For maximum density you go for 7.5T with CPP=78nm and for performance you choose the combination of track height and relaxed CPP to fit your product goals. My prediction is AMD has a design which needs max performance and they are not interested in the shrink but in the performance improvements with 12LP. Anyway I stand strongly by my predictions so lets see how PR turns out.

I think they'll stick with 9T cells rather than your 10.5T. However at this point we can only speculate so yeah, waiting it is.

 

[Vattila]

Perhaps I am building up too much optimism, but I think the upcoming "Zen+" 12LP Ryzen 2000-series on the desktop will surprise to the upside on frequency, and with the "Zen 2" 7LP Ryzen 3000-series, I think boost frequencies will be at 5+ GHz.

And, unlike Raghu78's speculation, that assumes AMD will need the HPC version of the 7LP process to achieve that, I think they'll manufacture the "Spaceship" die (presuming that is the successor to "Zeppelin") on the SoC version of the process, to cover all the products from Ryzen and Ryzen Threadripper to EPYC, just as with the reusable "Zeppelin" die.

I still think my calibration of that power-vs-performance chart from GlobalFoundries (posted earlier) makes the most sense, with the SoC version tuned for frequencies up to 5 GHz (at ~100 W for 8 cores), and the HPC version tuned for 5 GHz and beyond (at 110+ W, primarily for use by IBM).

AMD wants to ramp up volume, and I guess they want the yield and low cost a reusable die gives them. So, I expect more of the same on 7nm — just much improved in "multiple dimensions".

I expect a 12-core multi-use die for the initial 7LP process. A bigger 16-core die, for the rumoured 64-core EPYC, makes most sense on the more mature 7LP+ process, when EUV is brought into the process to improve yields and reduce the number of mask steps, and hence reduce cycle time and cost. So, I expect the 16-core die will be "Zen 3".

I also suspect AMD is working on a server APU with HBM for the HPC market, based on their exa-scale research. The 5-chip rumour (AdoredTV) may stem from related "chiplet" research. It seems too radical a change for the next-generation EPYC.

 

[Jan Olšan]

Note that this isn't just question of whether AMD chooses this cell for performance or that cell for density. There is also the question of money. In the past several years, we have seen that they were forced to use a single chip design for two generations (Richland, Godavari, BR) due to finances. AMD might simply not have enough resources and engineering manpower to do meaningful makeover of the cores between 14LPP and 12LP. They had to do work on Zen 2 during that time, keep in mind.

It is plausible (and I think the likely scenario) that this factor has forced them to port Zen to 12LP in a least-effort-possible manner, by leaving the core complex and as many other critical parts as possible without any changes, only doing new stuff in isolated and easier-to-validate parts. This way, they would exploit the fact that 12LP is basically tweaked 14LPP and should be compatible with designs made for 14LPP to some extent.

As a result, Pinnacle Ridge might be a chip that only receives some limited boost from the objective improvements in resulting silicon quality "iso-design", but doesn't get those bonuses offered by new cell libraries.

 

[CatMerc]

Note that this isn't just question of whether AMD chooses this cell for performance or that cell for density. There is also the question of money. In the past several years, we have seen that they were forced to use a single chip design for two generations (Richland, Godavari, BR) due to finances. AMD might simply not have enough resources and engineering manpower to do meaningful makeover of the cores between 14LPP and 12LP. They had to do work on Zen 2 during that time, keep in mind.

It is plausible (and I think the likely scenario) that this factor has forced them to port Zen to 12LP in a least-effort-possible manner, by leaving the core complex and as many other critical parts as possible without any changes, only doing new stuff in isolated and easier-to-validate parts. This way, they would exploit the fact that 12LP is basically tweaked 14LPP and should be compatible with designs made for 14LPP to some extent.

As a result, Pinnacle Ridge might be a chip that only receives some limited boost from the objective improvements in resulting silicon quality "iso-design", but doesn't get those bonuses offered by new cell libraries.

Doesn't match up with the work put into Pinnacle Ridge on other fronts. Cache latencies got tightened, IF latencies got tightened, memory controller is entirely different (don't ask me how I know that ), branch prediction got updated, and 12nm LP requires you to recompile and optimize the design either way. You can't just copy paste the design, even if it's lower effort than moving to a different node.

Whatever cell density they choose, it wasn't done for the sake of design cost savings, but rather what they think will be best for them in terms of die size/performance. Otherwise they'd just use GloFo's matured 14nm process.